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TLE8262-2E universal system basis chip hermes rev. 1.0 data sheet, rev. 1.0, may 2009 automotive power
data sheet 2 rev. 1.0, 2009-05-26 TLE8262-2E table of contents 1 hermes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2 state machine description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 general product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2 functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.4 current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 internal voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2 internal voltage regulator modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.3 internal voltage regulator modes with sbc mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.4 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7 external voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1 block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.2 external voltage regulator mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.3 external voltage regulator state by sbc mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.4 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8 high speed can transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.1 block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.2 high-speed can description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.3 can cell mode with sbc mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.4 failure detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.5 split circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.6 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9wk pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.1 block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.2 wake-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10 lin transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.1 block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.2 lin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.3 lin cell mode with sbc mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.4 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.5 failure detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.6 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11 supervision functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.1 reset function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table of contents
TLE8262-2E table of contents data sheet 3 rev. 1.0, 2009-05-26 11.2 watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12 interrupt function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 12.1 interrupt description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 12.2 interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 12.3 interrupt modes with sbc modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 12.4 interrupt application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 12.5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 13 limp home . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 13.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 13.2 limp home output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 13.3 activation of the limp home output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 13.4 release of the limp home output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 13.5 v cc1c undervoltage time-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 13.6 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 14 configuration select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 14.1 configuration select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 14.2 config hardware descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 15 serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 15.1 spi description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 15.2 corrupted data in the spi data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 15.3 spi input data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 15.4 spi output data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 15.5 spi data encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 15.6 spi output data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 15.7 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 16 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 16.1 zthja curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 16.2 hints for sbc factory flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 16.3 esd tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 17 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 18 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
pg-dso-36-38 type package marking TLE8262-2E pg-dso-36-38 TLE8262-2E data sheet 4 rev. 1.0, 2009-05-26 universal system basis chip hermes rev. 1.0 TLE8262-2E 1 hermes overview scalable system basis chip family ? eight products for complete scalable application coverage ? complete compatibility (hardware and software) across the family ? tle8264-2e (3lin), tle8263-2e (2lin) - 3 limp home outputs ? tle8264e (3lin), tle8263e (2lin) - 1 limp home output ? TLE8262-2E (1lin), tle8261-2e (no lin) - 3 limp home outputs ? tle8262e (1lin), tle8261e (no lin) - 1 limp home output basic features ? very low quiescent current in stop and sleep modes ? reset input, output ? power on and scalable undervoltage reset generator ? standard 16-bit spi interface ? overtemperature and short circuit protection ? short circuit proof to gnd and battery ? one universal wake-up input ? wide input voltage and temperature range ? cyclic wake in stop mode ? green product (rohs compliant) ?aec qualified description the devices of the sbc family are monolithic integrated circuits in an enhanced power package with identical software functionality and hardware features except for the number of lin cells. the devices are designed for can-lin automotive applications e.g. body controller, gateway applications. to support these applications, the system basis chip (sbc) provides the main functions, such as hs-can transceiver and lin transceivers for data transmission, low dropout voltage regulators (ldo) for an external 5 v supply, and a 16-bit serial peripheral interface (spi) to control and monitor the device. also implemented are a time-out or a window watchdog circuit with a reset feature, limp home circuitry output, and an undervoltage reset feature. the devices offer low power modes in order to support application that are connected permanent to the battery. a wake-up from the low power mode is possible via a message on the buses or via the bi-level sensitive monitoring/wake-up input as well as from the spi command. each wake-up source can be inhibited. the device is designed to withstand the severe conditions of automotive applications.
data sheet 5 rev. 1.0, 2009-05-26 TLE8262-2E hermes overview hs can transceiver ? compliant to iso 11898-2 and 11898-5 as well as sae j2284 ? can data transmission rate up to 1 mbaud ? supplied by dedicated input v cchscan ? low power mode management ? bus wake-up capability via can message ? excellent emc performance (very high immunity and very low emission) ? bus pins are short circuit proof to ground and battery voltage ? 8 kv esd gun test on canh / canl / split ? bus failure detection lin transceiver ? lin2.1 conformance, lin2.1 is back compatible to lin1.3 and lin2.0 ? sae j2602-2 conformance ? compatible to iso 9141 (k-l-line) ? transmission rate up to 20 kbaud, lin flash mode 115kbaud ? 8 kv esd gun test on bus pins voltage regulators ? low-dropout voltage regulator ? v cc1c , 200 ma, 5 v 2% for external devices, such as microcontroller and rf receiver ? v cc2 , 200 ma, 5 v 2% for external devices or the internal hs can cell ? v cc3 , current limitation by shunt resistor (up to 400 ma with 220 m ? shunt resistor), 5 v 4% with external pnp transistor; for example: to supply additional external can transceivers ? v cc1c , undervoltage time-out supervision ? reset output with integrated pull-up resistor ? time-out or window watchdog, spi configured ? watchdog timer from 16 ms to 1024 ms ? check sum bit for watchdog configuration ? reset due to watchdog failure can be inhibited with test pin (sbc sw development mode) interrupt management ? complete enabling / disabling of interrupt sources ? timing filter mechanism to avoid multiple / infinite interrupt signals limp home ? open drain limp home outputs ? dedicated internal logic supply ? maximum safety architecture for safety operation mode ? configurable fail-safe behavior ? dedicated side indicators signal 1.25hz 50% duty cycle ? dedicated pwm signal 100hz 20% duty cycle
data sheet 6 rev. 1.0, 2009-05-26 TLE8262-2E block diagram 2 block diagram the simplified block diagram illustrates only the basic elements of the sbc devices. please refer to the information for each device in the product family for more specific hardware configurations. figure 1 simplified block diagram v cc1c v cc2 gnd v cc3 spi interrupt control sbc state machine li m p hom e sdi sdo clk csn v cc1c v cc 2 v cc3base v cc3shunt v cc3ref can cell lin1 cell wk txd1 rxd1 bus 1 txd can rxd can v cchscan can_h split can_l wk ro reset generator int gnd v s v s block diagram_TLE8262-2E.vsd limp home lho_si lh_ pl/ test wake register v s v s v s vint . vint.
data sheet 7 rev. 1.0, 2009-05-26 TLE8262-2E pin configuration 3 pin configuration 3.1 pin assignments figure 2 pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 canh ro n.c. sdi clk sdo v cc3shunt gnd gnd gnd v cc1 c 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 v cc3ref n.c. v cc3 base n.c. n.c. lh_si wk rxd can txd can rxd lin txd lin limp home n.c. int n.c. vs bus1 csn exposed die pad lh_pl/test v cc2 TLE8262-2E dso 36 - exposed pad gnd v cchscan pinout_8262_2e.vsd split canl vs
data sheet 8 rev. 1.0, 2009-05-26 TLE8262-2E pin configuration 3.2 pin definitions and functions pin symbol function 1ro reset input/output; open drain output, integrated pull-up resistor; active low. 2csn spi chip select not input; csn is an active low input; serial communication is enabled by pulling the csn terminal low; csn input should be set to low only when clk is low; csn has an internal pull-up resistor and requires cmos logic level inputs. 3clk spi clock input; clock input for shift register; clk has an internal pull-down resistor and requires cmos logic level inputs. 4sdi spi data input; receives serial data from the control device; serial data transmitted to sdi is a 16-bit control word with the least significant bit (lsb) transferred first: the input has a pull-down resistor and requires cmos logic level inputs; sdi will accept data on the falling edge of the clk signal. 5sdo spi data output; this tri-state output transfers diagnostic data to the control device; the output will remain tri-stated unless the device is selected by a low on chip select not (csn). 6gnd ground 7n.c. not connected 8 v s power supply input; block to gnd directly at the ic with ceramic capacitor. ensure to have no current flow from pin8 to pin9. pin8 and pin9 can be directly connected. 9 v s power supply input; block to gnd directly at the ic with ceramic capacitor. ensure to have no current flow from pin8 to pin9. pin8 and pin9 can be directly connected. 10 bus1 lin bus 1; bus line for the lin interface, according to iso. 9141 and lin specification 2.1 as well as sae j2602-2. 11 v cc3 shunt pnp shunt; external pnp emitter voltage. 12 v cc3 base pnp base; external pnp base voltage. 13 gnd ground 14 v cc3ref external pnp output voltage 15 int interrupt output, configuration input; used as wake-up flag from sbc stop mode and indicating failures. active low. integrated pull up. during start-up used to set the sbc configuration. external pull-up sets config 1/3, no external pull-up sets config 2/4. 16 v cc1 c voltage regulator output; 5 v supply; to stabilize block to gnd with an external capacitor. 17 v cc2 voltage regulator output; 5 v supply; to stabilize block to gnd with an external capacitor. 18 v cchscan supply input; for the internal hs can cell. 19 canh can high line; high in dominant state. 20 split termination output; to support recessive voltage level of the bus lines. 21 canl can low line; low in dominant state. 22 gnd ground 23 txd can can transmit data input; integrated pull-up resistor. 24 rxd can can receive data output 25 txd lin lin transceiver data input; according to iso 9141 and lin specification 2.1 as well as sae j2602-2. integrated pull-up resistor.
data sheet 9 rev. 1.0, 2009-05-26 TLE8262-2E pin configuration 26 rxd lin lin transceiver data output; according to the iso 9141 and lin specification 2.1 as well as sae j2602-2; push-pull output; low in dominant state. 27 n.c. not connected 28 n.c. not connected 29 n.c. not connected 30 n.c. not connected 31 gnd ground 32 n.c. not connected 33 lh_si limp home side indicator; side indicators 1.25hz 50% duty cycle output; open drain. active low. 34 wk monitoring / wake-up input; bi-level sensitive input used to monitor signals coming from, for example, an external switch panel; also used as wake-up input; 35 limp home fail-safe function output ; open drain. active low. 36 lh_pl/test sbc sw development mode entry; connect to gnd for activation; integrated pull- up resistor. connect to v s or leave open for normal operation. limp home pulsed light output : brake/rear light 100hz 20% duty cycle output; open drain. active low. edp - exposed die pad; for cooling purposes only, do not use it as an electrical ground. 1) 1) the exposed die pad at the bottom of the package allows better dissipation of heat from the sbc via the pcb. the exposed die pad is not connected to any active part of the ic and can be left floating or it can be connected to gnd for the best emc performance. pin symbol function
data sheet 10 rev. 1.0, 2009-05-26 TLE8262-2E state machine 4 state machine 4.1 block description figure 3 power mode management sbc init mode (256ms max after reset relaxation) vcc1 on vcc2/3 off wd conf l.h. inact can inact lin inact sbc normal mode vcc1 on vcc2/3 on/off wd conf can conf lin conf sbc sw flash mode vcc1 on vcc2/3 on/off wd fixed can tx/rx lin flash mode sbc restart mode vcc1 on vcc2/3 on/off reset act. can waked or off sbc sleep mode vcc1 off vcc2/3 off wd off can wakable/ off lin wakable/ off sbc stop mode vcc1 on vcc2/3 on/off wd fixed/off can wakable/ off lin wakable/ off sbc fail-safe mode vcc1 off vcc2/3 off wd off l.h. act can sleep lin sleep sbc sw development mode vcc1 mode set vcc2/3 mode set wd mode set l.h. mode set can mode set lin mode set sbc factory flash mode vcc1 ext. vcc2/3 off wd off l.h. inact. can off lin off can, lin, wk wake-up or release of over temperature at vcc1 (wake-up event stored) (lh entry condition stored) 1st (config1) or 2nd (config3) wd trig failure in normal / stop / sw flash mode detection of falling edge at reset pin (any mode) or undervoltage reset at v cc1c (any mode) spi cmd or wd failed not reset clamped (high or low) or not undervoltage at vcc1 wk event stored lh entry condition stored or restart entry condition stored wake up event spi cmd spi cmd spi cmd spi cmd spi cmd spi cmd spi cmd reset (initiated by sbc ) wd trig first battery connection (por) and config0 not active first battery connection (por) and config 0 condition / event sbc action l.h. act/inact config 1/3: reset clamped low (any mode) config 2/4: reset clamped low (any mode) init mode not successful config 2/4: reset clamped high during restart or init mode l.h. act/inact l.h. act/inact l.h. act/inact l.h. act/inact 1st (config2) or 2nd (config4) wd trig failure in normal / stop / sw flash mode vcc1 over temperature shutdown or v s > v uv_on & undervoltage time out on v cc1 power mode managment.vsd config 1/3: reset clamped high during restart / init wd trig wd trig lin waked or off
data sheet 11 rev. 1.0, 2009-05-26 TLE8262-2E state machine 4.2 state machine description the system basis chip (sbc) offers ten operating modes: power on reset, init, normal, restart, software flash, sleep, stop, fail-safe, software development, and factory flash mode. the modes are controlled with one test pin and via three mode select bits ms2..0, within the spi. additionally, the sbc allows five configurations, accessed via two external pins and one spi bit. 4.2.1 configuration description table 1 provides descriptions and conditions for entry to the different configurations of the sbc. in sbc sw development mode, config 1 to 4 are accessible. 4.2.2 sbc power on reset (por) at v s > v uvon , the sbc starts to operate, by reading the test pin and then by turning on v cc1c . when v cc1c reaches the reset threshold v rt1 , the reset output remains activated for t rd1 and the sbc enters then the init mode. in the event that v s decreases below v uvoff , the device is completely disabled. for more details on the disable behavior of the sbc blocks, please refer to the chapter specific to each block. 4.2.3 sbc init mode at entering the sbc init mode, the sbc starts to read the test pin. the sbc starts-up in sbc init mode, and, after powering-up, waits for the microcontroller to finish its startup and initialization sequences. v cc2/3 are off and the watchdog is configurable but not active. can and lin modules are inactive and limp home output is inactive. from this transition mode, the sbc can be switched via spi command to the desired operating mode, sbc normal or software flash mode. if the sbc does not receive any spi command, or receive wrong spi command (i.e. not send the device to sbc normal or sbc sw flash mode) within a 256 ms time frame after the reset relaxation, it will enter into sbc restart mode and activate the limp home output. note: in init mode it is recommended to send one spi command that sets the device to normal mode, triggers the watchdog the first time and sets the required watchdog settings. table 1 sbc configuration configuration description test pin int pin wd to lh bit config 0 software development mode 0v n.a n.a config 1 after missing the wd trigger for the first time, the state of v cc1c remain unchanged, lh pin is active, sbc in restart mode open / v s external pull-up 0 config 2 after missing the wd trigger for the first time, v cc1c turns off, lh pin is active, sbc in fail-safe mode no ext. pull-up 0 config 3 after missing the wd trigger for the second time, the state of v cc1c remain unchanged, lh pin is active, sbc in restart mode external pull-up 1 config 4 after missing the wd trigger for the second time, v cc1c turns off, lh pin is active, sbc in fail-safe mode no ext. pull-up 1
data sheet 12 rev. 1.0, 2009-05-26 TLE8262-2E state machine 4.2.4 sbc normal mode sbc normal mode is used to transmit and receive can and lin messages. in this mode, v cc1c is always ?on? v cc2 and v cc3 can be turned-on or off by spi command. in normal mode the watchdog needs to be triggered. it can be configured via spi, window watchdog and time-out watchdog is possible (default value is time-out 256 ms). all the wake-up sources can be inhibited in this mode. the limp home output can be enabled or disabled via spi command. via spi command, the sbc can enter sleep, stop or software flash mode. a reset is triggered by the sbc when entering the software flash mode. it is recommended to send at first spi command the watchdog setting. please refer to chapter 13.4 . 4.2.5 sbc sleep mode during sbc sleep mode, the lowest power consumption is achieved by having the main and external voltage regulators switched-off. as the microcontroller is not supplied, the integrated watchdog is disabled in sleep mode. the last watchdog configuration is not stored. the can and lin modules are in their respective wake-capable or off modes and the limp home output is unchanged, as before entering the sleep mode. if a wake-up appears in this mode, the sbc goes into restart mode automatically. in sleep mode, not all wake-up sources should be inhibited, this is required to not program the device in a mode where it can not wake up. if all wake sources are inhibited when sending the sbc to sleep mode, the sbc does not go to sleep mode, the microcontroller is informed via the int output, and the spi bit ?fail spi? is set. the first spi output data when going to sbc normal mode will always indicate the wake up source, as well as the sbc sleep mode to indicate where the device comes from and why it left the state. note: do not change the transceiver settings in the same spi command that sends the sbc to sleep mode. 4.2.6 sbc stop mode the stop mode is used as low power mode where the c is supplied. in this mode the voltage regulator v cc1c remains active. the other voltage regulator ( v cc2/3 ) can be switched on or off. the watchdog can be used or switched off. if the watchdog is used the settings made in normal mode are also valid in stop mode and can not be changed. the can and lin modules are not active. they can be selected to be off or used as wake-up source. if all wake up sources are disabled, (can, lin, wk, cyclic wake) the watchdog can not be disabled, the sbc stays in normal mode and the watchdog continues with the old settings. if a wake-up event occurs the int pin is set to low. the c can react on the interrupt and set the device into normal mode via spi. there is no automatic transition to sbc normal mode. there are 4 options for sbc stop mode ? wd on (the watchdog needs to be served as in normal mode ? wd off (special sequence required see chapter 11.2.4 ) ? cyclic wake up with acknowledge (interrupt is sent after set time and needs to be acknowledged by spi read) ? cyclic wake-up, watchdog off (interrupt is sent after set time) cyclic wake-up feature sbc stop mode supports the cyclic wake-up feature. by default, the function is off. it is possible to activate the cyclic wake-up via ?cyclic wk on/off? spi bit. this feature is useful to monitor battery voltage, for example, during parking of the vehicle or for tracking rf data coming via the rf receiver. the cyclic wake-up feature sends an interrupt via the pin int to the c after the set time. the cyclic wake-up feature shares the same clock as the watchdog. the time base set in the spi for the watchdog will be used for the cyclic wake-up. the timer has to be set before activating the function. with the cyclic wake-up feature the watchdog is not working as known from the other modes. in the case that both functions (watchdog and cyclic wake-up) are selected, the cyclic wake-up is activated and each interrupt has to be acknowledged by reading the spi wake register before the next cyclic wake-up comes. otherwise, the sbc goes to sbc restart mode.
data sheet 13 rev. 1.0, 2009-05-26 TLE8262-2E state machine 4.2.7 sbc software flash mode sbc software flash mode is similar to sbc normal mode regarding voltage regulators. in this mode, the limp home output can be set to active low via spi and the communication on can and lin modules is activated to receive flash data. in the lin module the slope control mechanism is switched off. the watchdog configuration is fixed to the settings used before entering the sbc sw flash mode. when the device comes from sbc normal mode, a reset is generated at the transition. from the sbc software flash mode, the sbc goes into sbc restart mode, the config setting has no influence on the behavior. a mode change to sbc restart mode can be caused by a spi command, a time-out or window watchdog failure or an undervoltage reset. when leaving the sbc software flash mode a reset is generated. 4.2.8 sbc restart mode they are multiple reasons to enter the sbc restart mode and multiple sbc behaviors described in table 2 . in any case, the purpose of the sbc restart mode is to reset the microcontroller. ? from sbc sw flash mode, it is used to start the new downloaded code. ? from sbc normal, sbc stop mode and sbc sw flash mode it is reached in case of undervoltage on v cc1c , or due to incorrect watchdog triggering. ? from sbc sleep mode it is used to ramp up v cc1c after wake ? from sbc init mode, it is used to avoid the system to remain undefined. ? from sbc fail-safe mode it is used to ramp up v cc1c after wake or cool down of vcc1c. from sbc restart mode, the sbc goes automatically to sbc normal mode. the delay time t rdx is programmable by the ?reset delay? spi bit. the reset output (ro) is released at the transition. sbc restart mode is left automatically by the sbc without any microcontroller influence. the first spi output data will provide information about the reason for entering restart mode. the reason for entering restart mode is stored and kept until the microcontroller reads the corresponding ?lh0..2? or ?rm0..1? spi bits. in case of a wake up from sleep mode the wake source is seen at the interrupt bits (configuration select 000), an interrupt is not generated. entering or leaving the sbc restart mode will not result in deactivation of the limp home output (if activated). the first spi output data when going to sbc normal mode will always indicate the reason for the sbc restart event.
data sheet 14 rev. 1.0, 2009-05-26 TLE8262-2E state machine table 2 sbc restart mode entry reasons and actions sbc mode and configuration entering reason actions mode config lh output v cc1c ro spi out bits init mode n.a init mode time-out on remains on low lh 0..2 n.a. reset low from outside unchanged remains on low rm 0..1 config 1/3 reset clamped on remains on low lh 0..2 normal 1) 1) config 2 will never enter restart mode in case of wd failure but directly fail-safe mode n.a undervoltage reset unchanged ramping up low rm 0..1 config 1 wd trigger failure on remains on low lh 0..2 config 3 off after 1st on after 2nd rm 0..1 after 1st lh 0..2 after 2nd config 4 off after 1st rm 0..1 after 1st 2) 2) goes to fail-safe mode after the second consecutive failure n.a. reset low from outside unchanged remains on low rm 0..1 config 1/3 reset clamped on remains on low lh 0..2 software flash n.a undervoltage reset unchanged remains on low rm 0..1 n.a spi cmd unchanged remains on low rm 0..1 n.a wd trigger failure unchanged remains on low rm 0..1 n.a. reset low from outside unchanged remains on low rm 0..1 config 1/3 reset clamped on remains on low lh 0..2 sleep n.a wake-up event unchanged ramping up low wk bits register stop 1) n.a undervoltage reset unchanged ramping up low rm 0..1 config 1 wd trigger failure on remains on low lh 0..2 config 3 off after 1st on after 2nd rm 0..1 after 1st lh 0..2 after 2nd config 4 off after 1st rm 0..1 after 1st 2) n.a. reset low from outside unchanged remains on low rm 0..1 config 1/3 reset clamped on remains on low lh 0..2 fail-safe n.a. wake-up event on ramping up low lh 0..2 software development mode n.a undervoltage reset unchanged ramping up low rm 0..1 n.a. reset low from outside unchanged remains on low rm 0..1 config 1/3 reset clamped on remains on low lh 0..2
data sheet 15 rev. 1.0, 2009-05-26 TLE8262-2E state machine 4.2.9 sbc fail-safe mode in sbc fail-safe mode, all voltage regulators are off and the transceivers are in wake-capable mode. the limp home output is active. conditions to enter the sbc fail-safe mode are: ? watchdog trigger failure in configuration 2 or 4 ? v cc1c undervoltage time-out in any configuration if v s is above v lhuv range. ? temperature shutdown of v cc1c in any configuration. ? reset clamped in config. 2/4 in case of v cc1c overtemperature shutdown, the sbc will latch and wait to cool down below the thermal hysteresis, and will go back to sbc restart mode. in case of a wake-up event, the sbc will go to sbc restart mode (not in case of v cc1c overtemperature shutdown), storing the wake-up event and resetting the watchdog trigger failure counter. the first spi output data when going to sbc normal mode will always indicate the reason for the sbc fail-safe mode. 4.2.10 sbc software development mode if the test pin is connected to gnd (config 0 active) during powering-up, the sbc enters sbc software development mode. sbc software development mode is a super set of the other modes so it is possible to use all the modes of the sbc with the following difference. in sbc software development mode, no reset is generated and v cc1c is not switched off due to watchdog trigger failure. if a watchdog trigger failure occurs, it will be indicated by the int output (reset bit). the sbc fail-safe mode or sbc restart mode are not reached in case of wrong watchdog trigger but the other reasons to enter these modes are still valid. 4.2.11 sbc factory flash mode in this mode, the sbc is completely powered off and the microcontroller is supplied externally. the mode is detected when v cc1c is powered from external and the voltage on v s is not powered from external. the current flow out of v s must be limited to the maximum rating. the external supply voltage should be below the absolute maximum rating stated in chapter 5.1 . the reset can be driven by an external circuit, or pulled high with a pull-up resistor. note: please respect the absolute maximum ratings when the device is in sbc factory flash mode.
data sheet 16 rev. 1.0, 2009-05-26 TLE8262-2E general product characteristics 5 general product characteristics 5.1 absolute maximum ratings absolute maximum ratings 1) t j = -40 c to +150 c; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) 1) not subject to production test; specified by design pos. parameter symbol limit values unit test conditions min. max. voltages 5.1.1 supply voltage v s -0.3 40 v ? 5.1.2 supply voltage slew rate dv s/dt -0.5 5 v/s ? 5.1.3 regulator output voltage v cc1c/2/3 -0.3 5.5 v ? 5.1.4 can bus voltage (canh, canl) v canh/l -27 40 v ? 5.1.5 differential voltage canh, canl, split v diffesd -40 40 v canh-canl<|40 v|; canh-split<|40 v| canl-split<|40 v|; 5.1.6 input voltage at v cchscan v cchscan -0.3 5.5 v ? 5.1.7 voltage at split, wk v split -27 40 v ? 5.1.8 voltage at lh_pl/test v test,max -0.3 40 v ? 5.1.9 voltage at v cc3base , v cc3shunt, v cc3ref v cc3base -0.3 40 v ? 5.1.10 voltage at limp home (lh, lh_si pin) v lh -0.3 40 v ? 5.1.11 logic voltages input pin (sdi, clk, csn, txdlinx, txdcan) v i -0.3 v cc1c + 0.3v v0 v < v s < 28 v 0 v < v cc1c < 5.5 v 5.1.12 logic voltage output pin (sdo, ro, int, rxdlinx, rxdcan) v dri,rd -0.3 v cc1c + 0.3v v0 v < v s < 28 v 0 v < v cc1c < 5.5 v 5.1.13 lin line bus input voltages ? currents 5.1.14 reverse current on pin vs i vs -500 ? ma v s < v cc temperatures 5.1.15 junction temperature t j -40 150 c? 5.1.16 storage temperature t stg -55 150 c? esd susceptibility 5.1.17 electrostatic discharge voltage at busx canh, canl, split versus gnd v esd -6 6 kv 2) hbm (100 pf via 1.5 k ? ) 2) esd susceptibility human body model ?hbm? according to jesd22-a114 5.1.18 electrostatic discharge voltage v esd -2 2 kv 2) hbm (100 pf via 1.5 k ? ) 5.1.19 electrostatic discharge cdm corner pins (pin 1, 18, 19, 36) v esd_cdm _c -750 750 v 3) 3) esd susceptibility charged device model ?cdm? according to esda stm5.3.1 electrostatic discharge cdm v esd_cdm -500 500 v 3)
data sheet 17 rev. 1.0, 2009-05-26 TLE8262-2E general product characteristics note: stresses above the ones listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note: integrated protection functions are designed to prevent ic destruction under fault conditions described in the data sheet. fault conditions are considered as ?outside? normal operating range. protection functions are not designed for continuous repetitive operation. 5.2 functional range note: within the functional range the ic operates as described in the circuit description. the electrical characteristics are specified within the conditions given in the related electrical characteristics table. pos. parameter symbol limit values unit test conditions min. max. 5.2.1 supply voltage v s v uv off 28 v after v s rising above v uv on ; 1) 1) in the case v s < v uvoff , the sbc is switched off and will restart in init mode at next v s rising. 5.2.2 supply voltage v s v uv off 40 v 2) t pulse = 400 ms 40 v load dump; ri = 2 ? 2) during load dump, the others pins remains in their absolute maximum ratings 5.2.3 spi clock frequency f clkspi ?4 mhz 3) v s > 5.5 v 3) not subject to production test, specified by design 5.2.4 spi clock frequency f clkspi ? 1 mhz if v uv on > v s > v uv off ; 5.2.5 junction temperature t j -40 150 c? 5.2.6 undervoltage ?off? v uv off 34 v- 1) 5.2.7 undervoltage ?on v uv on 4.5 5.5 v - 1) 5.2.8 supply voltage for limp home output active v s_lh 5.5 40 v pull up to v s r lho = 40k ?
data sheet 18 rev. 1.0, 2009-05-26 TLE8262-2E general product characteristics 5.3 thermal characteristics pos. parameter symbol limit values unit test conditions min. typ. max. 5.3.1 junction ambient r thja_1l ?40 k/w 1) 3) 300 mm 2 cooling area 1) specified rthja value is according to jedec jesd51-2,-5,-7 at natural convection on fr4 single layer. the product (chip + package) was simulated on a 76.4 x 114.3 x 1.5 mm board. junction ambient r thja_4l ?25 k/w 2) 3) 2s2p + 600 mm 2 cooling area 2) according to jedec jesd51-2,-5,-7 at natural convection on 2s2p board for 2w. board: 76.2x114.3x1.5mm3 with 2 inner copper layers (35m thick)., with thermal via array under the exposed pad contacted the first inner copper layer and 600mm2 cooling are on the top layer (70m) 5.3.2 junction to soldering point r thjsp ?5?k/w 3) 3) not subject to production test; specified by design; thermal prewarning and shutdown junction temperatures; 5.3.3 v cc1c , thermal pre-warning on temperature t jpw 120 145 170 c- 3) 5.3.4 v cc1c , thermal prewarning hysteresis ? t pw ?25?k 3) 5.3.5 v cc1c, v cc2 thermal shutdown temperature t jsdvcc 150 185 200 c 3) 5.3.6 v cc1c , v cc2 thermal shutdown hysteresis ? t sdvcc ?35?k 3) 5.3.7 v cc1c , ratio of sd to pw temperature t jsdvcc/ t jpw ?1.20?? 3) 5.3.8 can transmitter thermal shutdown temperature t jsdcan 150 ? 200 c 3) 5.3.9 can transmitter thermal shutdown hysteresis ? t can ?10?k 3) 5.3.10 lin transmitter thermal shutdown temperature t jsdlin 150 ? 200 c 3) 5.3.11 lin transmitter thermal shutdown hysteresis ? t lin ?10?k 3)
data sheet 19 rev. 1.0, 2009-05-26 TLE8262-2E general product characteristics 5.4 current consumption v s = 5.5 v to 28 v; all outputs open; without v cc3 ; t j = -40 c to +150 c; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. pos. parameter symbol limit values unit test condition min. typ. max. normal mode; 5.4.1 current consumption for internal logic i vs_logic ?? 2masbc normal mode i cc1c = i cc2 = 0ma; can off mode; lin off mode 5.4.2 additional current consumption for can cell i vs_can ? ? 10 ma can normal mode; recessive state; v cc2 connected to v cchscan v txd = v cc1c ; without r l ? ? 12 ma can normal mode; dominant state; v cc2 connected to v cchscan v txd = low; without r l ; 5.4.3 additional current consumption per lin cell i vs_lin ? ? 3.0 ma lin normal mode; recessive state; without r l ; v txd = v cc1c ? ? 5.0 ma lin normal mode; dominant state; without r l ; v txd = low stop mode 5.4.4 current consumption i vs ? 58 75 a sbc stop mode; v s = 13.5 v; v cc1c ?on?; v cc2/3 ?off? can/lin wake capable; t j = 25c 65 85 t j = 85 c 1) ? 70 90 a sbc stop mode; v s = 13.5 v; v cc1c/2 ?on?; v cc3 ?off? can/lin wake capable; t j = 25c ? 78 100 t j = 85 c 1)
data sheet 20 rev. 1.0, 2009-05-26 TLE8262-2E general product characteristics sleep mode 5.4.5 current consumption, all wake up sources available. i vs_sleep_ sbc ? 28 40 a sbc sleep mode; t j = 25c v s = 13.5 v; v cc1c/2/3 ?off? can/lin wake capable; 32 50 t j = 85 c 1) 5.4.6 quiescent current reduction when one wake capable lin cell disabled i vs_sleep_ lin 0.5 1 ? a 1) sbc sleep mode; t j = 25c; v s = 13.5 v; v cc1c/2/3 ?off? can/lin 1_2 wake capable; lin3 off 5.4.7 quiescent current reduction when wake capable can cell disabled i vs_sleep_ can 512?a 1) sbc sleep mode; t j = 25c; v s = 13.,5 v; v cc1c/2/3 ?off? lin 1..3 wake capable; can off 1) not subject to production test; specified by design 5.4 current consumption (cont?d) v s = 5.5 v to 28 v; all outputs open; without v cc3 ; t j = -40 c to +150 c; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. pos. parameter symbol limit values unit test condition min. typ. max.
data sheet 21 rev. 1.0, 2009-05-26 TLE8262-2E internal voltage regulator 6 internal voltage regulator 6.1 block description figure 4 functional block diagram the internal voltage regulators are dual low-drop voltage regulators that can supply loads up to i cc1c/2_max . an input voltage up to v smax is regulated to v cc1c/2_nom = 5.0 v with a precision of 2%. due to its integrated reset circuitry, featuring two spi configurable power-on timing (t rdx ) and three spi configurable output voltages (v rtx ) monitoring, the device is well suited for microcontroller supply. the design enables stable operation even with ceramic output capacitors down to 470nf, with esr < 1 ? @ f = 10 khz. the device is designed for automotive applications, therefore it is protected against overload, short circuit, and overtemperature conditions. figure 4 shows the functional block diagram. if the v s voltage is lower than v uv_off , the dmos of the voltage regulator is switched to high impedance. the body diodes of the dmos might go into conduction when v cc1c or v cc2 > v s (no reverse protection). 6.2 internal voltage regulator modes it is possible to turn v cc1c via sbc modes and v cc2 activity on or off via spi command or by entering sbc modes. the limiting current for the both regulators is i cc1c_max / i cc2 . 6.3 internal voltage regulator modes with sbc mode depending on the sbc mode in use, v cc1c and v cc2 can be either on or off by definition, v cc2 can be also turned on or off, via spi. table 3 identifies the possible states of the voltage regulators, based on the various sbc modes. gnd internal regulator diagram.vsd overt emperature shutdown 1 bandgap reference charge pump vs state machine v cc 2 inh vref 1 vref v cc 1c
data sheet 22 rev. 1.0, 2009-05-26 TLE8262-2E internal voltage regulator 6.4 application information 6.4.1 timing diagram figure 5 shows the ramp up and down of the v s , and the dependency of v cc1c . at the first ramp up from sbc init mode, the reset threshold v rt and time t ro are set to the default value. see chapter 11.1 figure 5 ramp up / down of main voltage regulator an undervoltage time-out on v cc1c is implemented. refer to chapter 13 for more information on this function. 6.4.2 under voltage detection at v cc2 the v cc2 voltage regulator integrates an under voltage detection. when v cc2 voltage goes below v uv_vcc2 , the failure is indicated by an interrupt and the failure is reported into the diagnosis frame of the spi. table 3 internal voltage regulators states sbc mode vcc1c vcc2 init mode on off normal mode on on off sleep mode off off restart mode on unchanged software flash mode on on off stop mode on on off fail-safe mode off off t vcc1c t v uv off gnd ro t vs v uv on v rtx,r v rtx,f sbc off sbc init any mode sbc off
data sheet 23 rev. 1.0, 2009-05-26 TLE8262-2E internal voltage regulator 6.5 electrical characteristics v s = 5.5 v to 28 v; c cc1c = c cc2 = 470 nf; all outputs open; sbc normal mode; t j = -40 c to +150 c; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. pos. parameter symbol limit values unit test condition min. typ. max. voltage regulator; pin v cc1 c 6.5.1 output voltage v cc1c 4.9 5.0 5.1 v 0 ma < i cc1c <200 ma; 5.5 v < v s < 28 v; 6.5.2 line regulation ? v cc1c,li ?? 20mv6 v < v s < 16 v; i cc1c = 0 a 6.5.3 load regulation ? v cc1c,lo ?? 50mv5 ma < i cc1c <200 ma; v s = 6 v 6.5.4 power supply ripple rejection psrr ? 40 ? db v r = 1 vpp; f r = 100 hz; 1) 6.5.5 output current limit i cc1c max 200 ? 500 ma v cc1c = 4.5 v; power transistor thermally monitored; 6.5.6 drop voltage v dr vcc1c ?? 0.5v i cc1c = 150 ma; 2) voltage regulator; pin v cc2 6.5.7 output voltage v cc2 4.9 5.0 5.1 v 0 < i cc2 <200 ma; 5.5 v < v s < 28 v; 6.5.8 line regulation ? v cc2,li ?? 20mv6 v < v s < 16 v; i cc2 = 0 a; 6.5.9 load regulation ? v cc2,lo ?? 50mv5 ma < i cc2 <200 ma; v s = 6 v 6.5.10 power supply ripple rejection psrr ? 40 ? db v r = 1 vpp; f r = 100 hz; 1) 6.5.11 output current limit i cc2 200 ? 500 ma v cc2 = 4.5 v; power transistor thermally monitored; 6.5.12 drop voltage v dr_vcc2 ?? 0.5v i cc2 = 150 ma; 2) 6.5.13 under voltage detection on v cc2 v uv_vcc2 4.5 4.65 4.8 v v cc2 falls until int = low 1) specified by design; not subject to production test. 2) measured when the output voltage has dropped 100 mv from the nominal value obtained at v s = 13.5 v. specified drop voltage for vs > 4 v.
data sheet 24 rev. 1.0, 2009-05-26 TLE8262-2E external voltage regulator 7 external voltage regulator 7.1 block description v cc3 is activated via spi. the external voltage regulator circuitry is designed to drive an external pnp transistor to increase output current flexibility. four pins are used: v s , v cc3base , v cc3shunt and v cc3ref . one transistor is tested during production. an input voltage up to v smax is regulated to v q,nom = 5.0 v with a precision of 4% . the output current of the transistor is monitored via an external shunt resistor. the state of v cc3 is reported in the diagnostic spi register. when battery voltage is below the minimum operating battery voltage v s < v vextuv , the external voltage regulator switches off. figure 7 shows the behavior during this phase. the shunt is used for overcurrent limitation. if this feature is not needed, connect pins v cc3shunt and v s together . since the junction temperature of the external pnp transistor cannot be read, it cannot be protected against over temperature by the sbc, and so the thermal behavior has to be checked by the application. figure 6 functional block diagram 7.2 external voltage regulator mode it is possible to turn the v cc3 on or off via spi command, depending on the sbc modes. table 4 identifies the possible states, based on the different sbc modes. 7.3 external voltage regulator state by sbc mode table 4 shows the possible states of the v cc3 external voltage regulator as a function of the sbc mode. table 4 external voltage regulator state by sbc mode sbc mode v cc3 init mode off normal mode on off sleep mode off restart mode unchanged sw flash mode on off stop mode on off fail-safe mode off r be v s -v cc3shunt > v shunt_threshold v ref state machine + - external voltage diagram .vsd i cc3base vcc 3ref vcc 3base vcc3 shunt v s
data sheet 25 rev. 1.0, 2009-05-26 TLE8262-2E external voltage regulator 7.4 application information 7.4.1 timing information figure 7 shows the typical timing, ramp up and ramp down of the external voltage regulator, in regards to the v s pin. figure 7 supply voltage management 7.4.2 external components during production test, the listed parameter are tested with the pnp transistor mjd253 from on semi. characterization is done with the bcp52-16 from infineon ( i cc3 <200 ma). other pnp transistors can be used. function must be checked in the application. figure 8 shows the hardware set up used. figure 8 hardware set up vcc3 t v uv_off gnd t vs v cc 3 under voltage m anagm ent v cc 3 .vsd v vextuv spi external voltage diagram_appli_note.vsd r shunt t1 c 2 c 1 v s vcc3base vcc3ref r be vcc3shunt v s v s -v cc3shunt > v shunt_threhold v ref state machine + - i cc3base v cc3 i cc3
data sheet 26 rev. 1.0, 2009-05-26 TLE8262-2E external voltage regulator 7.4.3 calculation of r shunt the maximum current i cc3max where the limit starts and the bit i cc3 > i cc3max is set is determined by the shunt resistor r shunt and the output current shunt voltage threshold v shunt_threshold . the resistor can be calculated as following 7.4.4 unused pins in case the vcc3 is not used in the application, it is recommended to connect the unused pins of vcc3 as followed. connect vcc1shunt to vs. (it is also possible to leave the pin open) leave vcc3base open leave vcc3ref open do not enable the vcc3 via spi as this leads to increased current consumption. table 5 bills of material for the v cc3 function device vendor reference / value c 2 murata 10f/10v gcm31cr71aa106k r shunt -220m ? t 1 on semi mjd253 r shunt u shunt_threshold i cc3max -------------------------------------- =
data sheet 27 rev. 1.0, 2009-05-26 TLE8262-2E external voltage regulator 7.5 electrical characteristics v s = 5.5 v to 28 v; sbc normal mode; all outputs open; t j = -40 c to +150 c; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. pos. parameter symbol limit values unit test condition min. typ. max. parameters independent from test set-up 7.5.1 external regulator control drive current capability i cc3base 20 70 ma v cc3base = 28v 7.5.2 input current v cc3ref i cc3ref 10 25 50 a v cc3ref = 5 v 7.5.3 input current v cc3 shunt pin i cc3shunt 10 25 50 a v cc3shunt = v s 7.5.4 v cc3 undervoltage detection v cc3,uv 4.0 4.25 4.5 v ? 7.5.5 v cc3 undervoltage detection hysteresis v cc3,uv, hys 20 100 250 mv 7.5.6 output current shunt voltage threshold v shunt_thr eshold 88 110 130 mv 1) 1) threshold at which the current limitation starts to operate. 7.5.7 current increase regulation reaction time t riinc -- 5s v cc3 = 6v to 0v; i cc3base,50% = 20ma figure 9 7.5.8 current decrease regulation reaction time t ridec -- 5s v cc3 = 0v to 6v; i cc3base,50% = 20ma figure 9 7.5.9 leakage current of v cc3base when vcc3 disabled i cc3base_lk -- 5a v cc3base = v s t j = 25c 7.5.10 leakage current of v cc3ref when vcc3 disabled i cc3ref_lk -2 0 2 a v cc3ref = 5v t j = 25c 7.5.11 leakage current of v cc3shunt when vcc3 disabled i cc3shunt_l k -- 5a v cc3shunt = v s t j = 25c 7.5.12 base to emitter resistor r be 50 100 200 k ? v cc3base = v s - 0.3v v cc3 off 7.5.13 external regulator minimum vs voltage v vextuv 4.5 - 5.5 v 7.5.14 external regulator minimum vs voltage hysteresis v vextuvhy s - 0.2 - v parameters dependent on the test set-up, according to the figure 8 7.5.15 external regulator output voltage v cc3 4.8 5 5.2 v 0 ma < i cc3 <400 ma; 5.5 v < v s < 28 v; 2) 2) tolerance includes load regulation and line regulation. 7.5.16 load regulation ? v cc3,lo - - 50 mv 2 ma < i cc3 <200 ma; 7.5.17 line regulation ? v cc3,li -- 50mv6 v < v s <16 v;
data sheet 28 rev. 1.0, 2009-05-26 TLE8262-2E external voltage regulator timing diagram for regulator reaction time ?current increase regulation reaction time? and ?current decrease regulation reaction time? figure 9 regulator reaction time t v cc3 t i ccbase i cc3base,50% t rlinc t rldec
data sheet 29 rev. 1.0, 2009-05-26 TLE8262-2E high speed can transceiver 8 high speed can transceiver 8.1 block description figure 10 functional block diagram 8.2 high-speed can description the controller area network (can) transceiver part of the sbc provides high-speed (hs) differential mode data transmission (up to 1 mbaud) and reception in automotive and industrial applications. it works as an interface between the can protocol controller and the physical bus lines compatible to iso/dis 11898-2 and 11898-5 as well as sae j2284. the can transceiver offers low power modes to reduce current consumption. this supports networks with partially powered down nodes. to support software diagnostic functions, a can receive-only mode is implemented. it is designed to provide excellent passive behavior when the transceiver is switched off (mixed networks, clamp15/30 applications). a wake-up from the can wake capable mode is possible via a message on the bus. thus, the microcontroller can be powered down or idled and will be woken up by the can bus activities. refer to figure 11 for a description of the matching of the transceiver modes with the sbc mode. the can transceiver is designed to withstand the severe conditions of automotive applications and to support 12 v applications. txd can output stage driver temp.- protection canh canl + timeout rxd can receiver mux v cc1c v spi mode control to spi diagnostic gnd rxd diag split r split v split cchs can can block .vsd v cchscan v cc1c r td wake receiver vs
data sheet 30 rev. 1.0, 2009-05-26 TLE8262-2E high speed can transceiver 8.2.1 can normal mode to transfer the can transceiver into the can normal mode, an spi word must be sent. this mode is designed for normal data transmission/reception within the hs can network. it can be accessed in normal mode of the sbc, as well as in sbc software flash mode, and sbc software development mode. transmission the signal from the microcontroller is applied to the txdcan input of the sbc. the bus driver switches the canh/l output stages to transfer this input signal to the can bus lines. reduced electromagnetic emission to reduce electromagnetic emissions (eme), the bus driver controls canh/l slopes symmetrically. reception analog can bus signals are converted into digital signals at rxd via the differential input receiver. in can normal and can receive only mode, the split pin is used to stabilize the recessive common mode signal. the rxd pin is diagnosed and the detected failure is reported to the spi diagnostic register. 8.2.2 can wake capable mode this mode, which can be used in sbc stop, sleep, restart and normal modes by programming via spi and is automatically accessed in sbc fail-safe mode, is used to monitor bus activities. a wake up signal on the bus results in different behavior of the sbc, as described in table 6 . after wake-up the transceiver can be switched to can normal mode for communication. to enable the can wakeable mode after a wake via can, the can transceiver must be switched to can normal mode, can receive only mode or can off, before switching to can wakeable mode again. wake-up in sbc sleep mode wake-up is possible via a can message (filtering time t > t wu ), it automatically transfers the sbc into the sbc restart mode and from there to normal mode the rxd pins in set to low, see figure 11 . the microcontroller is able to detect the low signal on rxd and to read the wake source out of the ?wake register interrupt? register (000) via spi. no interrupt is generated when coming out of sleep mode. table 6 action due to a can wake up sbc mode sbc mode after wake vcc1c int rxd int. bit wk can sleep mode restart mode ramping up high low 1 stop mode stop mode on low 1) 1) when not masked via spi low 1 restart mode restart mode ramping up / on high low 1 fail-safe mode restart mode ramping up high low 1 normal mode normal mode on low 1) low 1
data sheet 31 rev. 1.0, 2009-05-26 TLE8262-2E high speed can transceiver figure 11 timing during transition from sleep to normal mode wake-up in sbc stop mode in sbc stop mode, if a wake-up is detected, it is signaled by the int output and by the ?wk can? spi bit. it is also signaled by rxdcan put to low. the microcontroller should set the device to sbc normal mode, there is no automatic transition to normal mode. in normal mode the transceiver can be enabled via spi. wake-up in sbc restart or sbc fail-safe mode in sbc restart or sbc fail-safe mode, if a wake-up is detected, it is signaled by the ?wk can? spi bit. wake-up in sbc normal mode in sbc normal mode, if a wake-up is detected, it is signaled by the ?wk can? spi bit and int output, and rxd remains low. can_h can_l vdiff v cc1c/ hscan rxd sbc normal mode t wu bus off bus wait wake pattern communication starts ro application with sleep .vsd sbc sleep mode sbc restart t rox t t t t t spi command can wake capable mode can waked can normal mode
data sheet 32 rev. 1.0, 2009-05-26 TLE8262-2E high speed can transceiver 8.2.3 can off mode can off mode, which can be accessed in the sbc stop, sleep, restart and normal modes, and automatically accessed in sbc init and factory flash modes, is used to completely stop can activities. in can off mode, a wake up event on the bus will be ignored. 8.2.4 can receive only mode in can receive only mode (rxd only), the driver stage is de-activated but reception is still operational. this mode is accessible by an spi command. 8.2.5 can cell in disabled state during disable state, when v s < v uv_off , the can cell does not have enough supply voltage. in this state, the canh and canl pins are set to high impedance, to guarantee passive behavior. the maximum current that can flow in the canh and canl pins in this mode are specified by i canh,lk and i canl,lk . 8.3 can cell mode with sbc mode table 7 shows all the can modes accessible to the current sbc mode. automatic transition from one can mode to an other is only allowed in the same column. . 8.3.1 sbc normal transition to sleep or stop mode during the transition from sbc normal to sleep or stop modes, the receiver module is deactivated and replaced by the low power mode receiver for wake-up capability. the next message can be only a wake-up call. it is possible to set the sbc directly from sbc normal mode (with can normal mode) to sbc sleep or stop mode, but this is not recommended, because a wake pattern on the can network that could occurs during spi communication could get lost. it is preferable, in sbc normal mode to first send the can transceiver into can wake capable mode, and then set the entire device to sbc sleep or stop mode. in the unlikely case that the device would see a wake up call during the transmission order ?sbc go to sleep?, the device will store this event and bypass the ?sbc go to sleep? command to go back into sbc restart mode. do not change the transciever setting with the same spi command that is used to sent the device to sleep mode. 8.3.2 transition from sbc sleep to other modes in sbc sleep mode, a wake-up on the can cell will set the sbc to restart mode automatically if the can wake capable mode of the sbc is selected via spi. figure 11 shows the typical timing. table 7 hs can states, based on sbc modes sbc mode can mode init mode off normal mode off wake capable normal receive only stop mode off wake capable sleep mode off wake capable restart mode off wake capable fail-safe mode wake capable sw flash mode normal
data sheet 33 rev. 1.0, 2009-05-26 TLE8262-2E high speed can transceiver 8.4 failure detection all failures are reported in the spi diagnostic encoder, the txd time-out is reported as txd shorted to gnd. in case of local failure and bus dominat clamped failure, the transceiver is automatically switched to the can receive only mode. 8.4.1 txd time-out feature if the txd signal is dominant for a time t > t txd , the txd time-out function deactivates the transmission of the signal at the bus. this is implemented to prevent the bus from being blocked permanently due to an error. the transmission is released after switching the can to active mode via spi. refer to figure 12 . figure 12 txd time-out diagram 8.4.2 bus dominant clamping if the hs can bus signal in dominant for a time t > t bus_to , a bus dominant clamping is detected. the can transceiver is switched to receive only mode. the failure is signaled via spi. if the bits are not masked the int pin is set to low. for operation the transceiver needs to be switched back to normal mode via spi. 8.4.3 txd to rxd short circuit feature similar to the txd time-out, a txd to rxd short circuit would also block the bus communication. to avoid this, the can transceiver provides txd to rxd short circuit detection. in this case, it is recommended to switch off the sbc hs can supply (e.g. v cc2 ) via spi command to prevent disturbances on the can bus. this failure is reported into the diagnostic frame of the spi. the int pin is set low if not disabled via spi. the transmitter is automatically inhibited and goes back to normal operation after a spi command. 8.4.4 overtemperature the driver stages are protected against overtemperature. exceeding the shutdown temperature results in deactivation of the can transceiver. the can transceiver is activated gain after cooling down, the device stays in can active mode. to avoid a bit failure after cooling down, the signals can be transmitted again only after a dominant to recessive edge at txd. figure 13 shows how the transmission stage is deactivated and activated again. first, an overtemperature condition causes the can transceiver to be deactivated. after the overtemperature condition is no longer present, the transmission is released automatically after the txd bus signal has changed to recessive level. t txd can t v cc1c v diff txd time -out interrupt gnd t txd_to txd timeout .vsd spi setting : can normal mode
data sheet 34 rev. 1.0, 2009-05-26 TLE8262-2E high speed can transceiver figure 13 release of the transmission after overtemperature 8.4.5 permanent rxd recessive clamping if the rxd signal is permanently recessive (such as shorted to v cc1c ), although there is a message sent on the bus, the host microcontroller of this transceiver could start a message at any time because the bus appears to be idle. to prevent this node from disturbing communication on the bus, the sbc offers permanent rxd recessive clamping. if the rxd signal is permanently recessive, the failure is diagnosed and the transmitter is deactivated as long as the error occurs. the transmitter is reactivated after an spi command. 8.4.6 v cchscan undervoltage the can transceiver cell has no dedicated under voltage detection and use the v cc2 or v cc3 under voltage circuitry. the c can switch of the can in case of undervoltage. 8.4.7 bus failures in case one of the following bus failures is detected by the sbc the interrupt bit can bus is set to ?1? and an interrupt is generated, if not masked. the can transceiver does not change the mode due to a detected bus failure. bus failures ? canh short to gnd ? canh short to vs ? canh short to vcc ? canl short to gnd ? canl short to vs ? canl short to vcc a short of canh to canl is detected by the microcontroller as the signal sent on txd is not received on rxd. 8.5 split circuit split circuitry is activated during can normal and receive only mode and de-activated (split pin high ohmic) during can wake capable and off modes. the split pin is used to stabilize the recessive common mode signal in normal mode and rxd only mode. this is achieved with a stabilized voltage of 0.5 x v cchscan typical at split. a correct application of the split pin is shown in figure 14 . the split termination for the left and right nodes is implemented with two 60 ? resistors and one 10 nf capacitor. the center node in this example is a stub node and the recommended value for the split resistances is 1.5 k ? . t failure overtemp t on txd can v diff t recessive dominant v cc1c overtemperature gnd off r d
data sheet 35 rev. 1.0, 2009-05-26 TLE8262-2E high speed can transceiver in the case the application doesn?t request the split pin feature, the pin has to be left open. figure 14 application example for the split pin . canh canl split termination split termination can bus canh canl split split 60ohm 60ohm 60ohm 60ohm 10nf 10nf tle 8264 canh canl split 10nf split termination at stub 1,5 kohm 1,5 kohm tle 6251 ds tle 6251 g nerr
data sheet 36 rev. 1.0, 2009-05-26 TLE8262-2E high speed can transceiver 8.6 electrical characteristics 4.75 v < v cchscan < 5.25 v; v s = 5.5 v to 28 v; r l = 60 ? ; can normal mode; t j = -40 c to +150 c; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. pos. parameter symbol limit values unit test condition min. typ. max. can bus receiver 8.6.1 differential receiver threshold voltage, recessive to dominant edge v diff,rd_n ? 0.80 0.90 v v diff = v canh - v canl can normal mode 8.6.2 differential receiver threshold voltage, dominant to recessive edge v diff,dr_n 0.50 0.60 ? v v diff = v canh - v canl can normal mode 8.6.3 common mode range cmr -12 ? 12 v ? 8.6.4 differential receiver hysteresis v diff,hys_n ? 110 ? mv can normal mode 8.6.5 canh, canl input resistance r i 10 20 30 k ? recessive state 8.6.6 differential input resistance r diff 20 40 60 k ? recessive state 8.6.7 wake-up receiver threshold voltage, recessive to dominant edge v diff, rd_w ? 0.8 1.15 v can wake capable mode 8.6.8 wake-up receiver threshold voltage, dominant to recessive edge v diff, dr_w 0.4 0.7 ? v can wake capable mode 8.6.9 wake-up receiver differential receiver hysteresis v diff, hys_w ? 120 ? mv can wake capable mode
data sheet 37 rev. 1.0, 2009-05-26 TLE8262-2E high speed can transceiver can bus transmitter 8.6.10 canh/canl recessive output voltage v canl/h 2.0 ? 3.0 v can normal mode no load 8.6.11 canh, canl recessive output voltage difference v diff = v canh - v canl v diff_r_n -500 ? 50 mv can normal mode v txd = v cc1c ; no load 8.6.12 canl dominant output voltage v canl 0.5 ? 2.25 v can normal mode v txd = 0 v; v cchscan = 5 v 8.6.13 canh dominant output voltage v canh 2.75 ? 4.5 v can normal mode v txd = 0 v; v cchscan = 5 v 8.6.14 canh, canl dominant output voltage difference v diff = v canh - v canl v diff_d_n 1.5 ? 3.0 v can normal mode v txd = 0 v; v cchscan = 5 v 8.6.15 canh, canl dominant output voltage difference v diff = v canh - v canl v diff_d_n 1.5 ? 3.0 v can normal mode v txd = 0 v; v cchscan = 5 v r l = 50 ? 8.6.16 canh short circuit current i canhsc -200 -80 -50 ma can normal mode v canhshort = 0 v 8.6.17 canl short circuit current i canlsc 50 80 200 ma can normal mode v canlshort = 18 v 8.6.18 leakage current i canh,lk i canl,lk ?2?a v s = v cchscan = 0 v; 0 v < v canh,l < 5 v split termination output; pin split 8.6.20 split output voltage v split 0.3 v cchscan 0.5 v cchscan 0.7 v cchscan v can normal mode -500 a < i split < 500 a 8.6.21 leakage current i split -5 0 5 a can wake capable mode; -27 v < v split < 40 v 8.6.22 split output resistance r split ? 600 ? ? ? 1) receiver output rxd 8.6.23 high level output voltage v rxd,h 0.8 v cc1c ??v can normal mode i rxd(can) = -2 ma; 8.6.24 low level output voltage v rxd,l ??0.2 v cc1c v can normal mode i rxd(can) = 2 ma; transmission input txd 8.6.26 high level input voltage threshold v td,h ??0.7 v cc1c v can normal mode recessive state 8.6.27 low level input voltage threshold v td,l 0.3 v cc1c ? ? v can normal mode dominant state 8.6 electrical characteristics (cont?d) 4.75 v < v cchscan < 5.25 v; v s = 5.5 v to 28 v; r l = 60 ? ; can normal mode; t j = -40 c to +150 c; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. pos. parameter symbol limit values unit test condition min. typ. max.
data sheet 38 rev. 1.0, 2009-05-26 TLE8262-2E high speed can transceiver 8.6.28 txd input hysteresis v td,hys ?0.12 v cc1c ?mv 1) 8.6.29 txd pull-up resistance r td 20 40 80 k ? ? dynamic can-transceiver characteristics 8.6.30 min. dominant time for bus wake-up t wu 0.75 3 5 s can wake capable mode 8.6.31 propagation delay txd-to-rxd low (recessive to dominant) t d(l),tr ? 150 255 ns can normal mode c l = 47 pf; r l = 60 ? ; v cchscan = 5 v; c rxd = 15 pf 8.6.32 propagation delay txd-to-rxd high (dominant to recessive) t d(h),tr ? 150 255 ns can normal mode c l = 47 pf; r l = 60 ? ; v cchscan = 5 v; c rxd = 15 pf 8.6.33 propagation delay txd low to bus dominant t d(l),t ? 50 120 ns can normal mode c l = 47 pf; r l = 60 ? ; v cchscan = 5 v 8.6.34 propagation delay txd high to bus recessive t d(h),t ? 50 120 ns can normal mode c l = 47 pf; r l = 60 ? ; v cchscan = 5 v 8.6.35 propagation delay bus dominant to rxd low t d(l),r ? 100 135 ns can normal mode c l = 47 pf; r l = 60 ? ; v cchscan = 5 v; c rxd = 15 pf 8.6.36 propagation delay bus recessive to rxd high t d(h),r ? 100 135 ns can normal mode c l = 47 pf; r l = 60 ? ; v cchscan = 5 v; c rxd = 15 pf 8.6.37 txd permanent dominant time-out t txd_to 0.3 0.6 1.0 ms can normal mode 8.6.38 bus dominant time-out t bus_to 0.3 0.6 1.0 ms can normal mode 1) 1) not subject to production test; specified by design. 8.6 electrical characteristics (cont?d) 4.75 v < v cchscan < 5.25 v; v s = 5.5 v to 28 v; r l = 60 ? ; can normal mode; t j = -40 c to +150 c; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. pos. parameter symbol limit values unit test condition min. typ. max.
data sheet 39 rev. 1.0, 2009-05-26 TLE8262-2E high speed can transceiver figure 15 timing diagrams for dynamic characteristics t d(l), r t v di ff t d(l), t r t d(h), r t d(h), t r t d(l), t t gnd v txd v cc1c t d(h), t v dif f , rd_n v diff, dr_n t gnd 0.2 x v cc1c 0.8 x v cc1c v rxd v cc1c can dynamic characteristics.vsd
data sheet 40 rev. 1.0, 2009-05-26 TLE8262-2E wk pin 9wk pin 9.1 block description figure 16 functional block diagram the internal voltage regulator ( v cc1c ) and the entire sbc can wake up by changing the wake input voltage. the wk input pin is a bi-level sensitive input. this means that both transitions, high to low and low to high, result in a wake-up. the filtering time is t wk, f. the wake-up capability can be enabled or disabled via spi command. in case of reverse polarity, no special protection must be set if the absolute maximum rating is respected. when the sbc is below the minimum v uvoff , (sbc off mode) the pin wk is at high impedance; a wake event will be ignored. the state of the wk pin (low or high) can always be read in normal mode, stop mode and sw flash mode at the bit wk state. when setting the bit ?wk pin on/off? to 1, the device wakes up from sleep mode with a high to low or low to high transition. from fail-safe mode the device will always go to restart mode with a high to low or low to high transition. if the bit ?wk pin on/off? is set to 1 in normal, stop or sbc sw flash mode the interrupt bits ?wk 0 wk pin? and/or ?wk 1 wk pin? are set in case of a change on the wk pin and an interrupt is generated if not masked. with the bits ?wk 0 wk pin? and ?wk 1 wk pin? the interrupt for low to high transition and high to low transition can be masked separately. 9.2 wake-up timing figure 17 shows typical wake-up timing and parasitic filtering. the filtering time is t wk, f. . this is used to avoid a parasitic wake-up due to emc disturbances. specifically, the voltage transition on pin wk must be higher than the v wk,th and longer than t wk,f to be understood as a wake-up signal. internal supply i pu_mon wake.vsd i pd_mon i wk state machine
data sheet 41 rev. 1.0, 2009-05-26 TLE8262-2E wk pin figure 17 wake-up timing 9.2.1 transition from normal to sleep mode. the sbc can not be sent from normal mode to sleep mode with uncleared interrupt in the wk interrupt bits ?wk 0 wk pin? and ?wk 1 wk pin?. this is implemented to avoid that a wake information from the wk pin gets lost during the transition from normal to sleep mode. if a wake up appears during the c sets the sbc to sleep mode, the sbc will wake up directly after going to sleep mode. there is no difference if the bits ?wk 0 wk pin? or ?wk 1 wk pin? bit were set during the transition or were just not cleared before sending the spi command for sleep mode, the sbc will wake-up after entering the sleep mode. therefore it always needs to be ensured that the bits are cleared before sending the sbc to sleep mode. v wk,th t v wk t wk,f no wake event wake event v wk,th w ake pin diagram .vsd t wk,f
data sheet 42 rev. 1.0, 2009-05-26 TLE8262-2E wk pin 9.3 electrical characteristics v s = 5.5 v to 28 v; t j = -40 c to +150 c; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. pos. parameter symbol limit values unit test condition min. typ. max. 9.3.1 wk input threshold voltage v wk,th 23 4v? 9.3.2 input hysteresis v i, hys. 0.1 ? 0.7 v 9.3.3 wk filter time t wk, f 10 ? 25 s ? 9.3.4 input current i wk -2 ? 2 a v wk = 0 v; v wk > 5v 9.3.5 wk pin pull up current i pu_mon -30 ? -3 a v wk = 3.8 v 9.3.6 wk pin pull down current i pd_mon 3? 30a v wk = 2 v
data sheet 43 rev. 1.0, 2009-05-26 TLE8262-2E lin transceiver 10 lin transceiver the sbc includes up to three lin blocks, but this chapter describes only one because all three lin block are completely identical. 10.1 block description figure 18 functional block diagram 10.2 lin description the lin transceiver cells of the sbc is an interface between the protocol controller and the physical bus. it is especially suitable for driving the bus line in lin systems in automotive and industrial applications. it is compatible to lin 2.1 as well as sae j2602-2. to reduce current consumption, the lin transceiver offers a lin wake capable mode and a lin off mode. the lin transceiver has a bus short to gnd feature implemented to avoid a battery discharge. the transceiver offers very good emc performance within a broad frequency range independent of battery voltage. this is achieved by implementing a slope control mechanism based on a constant slew rate. in case the v s < v uvoff , the lin bus pin has high impedance and the maximum current which can flow in is set to i buslk 10.2.1 lin normal mode in this mode, it is possible to transmit and receive messages on each busx. the lin transceiver enters the lin normal mode after the microcontroller sends an spi word (see chapter 15 ) and also by entering sbc software flash mode. driver temp.- protection current limit output stage txd input receiver rxdx busx txdx v s r bus filter timeout l i n bl ock. vsd r td vcc1c to spi diagnostic rxd diag spi mode control vcc1c wake receiver vs
data sheet 44 rev. 1.0, 2009-05-26 TLE8262-2E lin transceiver 10.2.2 slope selection the lin transceiver offers a lin low slope mode for 10.4 kbaud communication and a lin normal slope mode for 20 kbaud communication. the only difference is the behavior of the transmitter. in lin low slope mode, the transmitter uses a lower slew rate to further reduce the eme compared to normal mode. this complies with sae j2602 requirements. the selection is done for all transceivers at the same time so that the chip is working in either lin low slope mode or in lin normal slope mode. by default, the device works in lin low slope mode. the selection of lin normal slope mode is done by an spi word. the selection is accessible in sbc normal mode only. 10.2.3 lin off mode in this mode, the lin transceiver is completely disabled. only an spi command can reactivate the lin cell. this mode is accessible in sbc normal, stop, and sleep modes and is the default behavior in sbc init mode. 10.2.4 lin wake capable mode this mode, which can be used in sbc stop, sleep, restart and normal modes by programming via spi and is automatically accessed in sbc fail-safe mode, is used to monitor bus activities. a wake up signal on the bus results in different behavior of the sbc, as described in table 8 . after wake-up the transceiver can be switched to lin normal mode for communication. to enable the lin wakeable mode after a wake via this lin tranceiver, the deticated lin transceiver must be switched to lin normal mode, lin receive only mode or lin off, before switching to lin wakeable mode again. wake-up in sbc sleep mode wake-up is possible via a lin message (filtering time t > t wk,bus ), it automatically transfers the sbc into the sbc restart mode and from there to normal mode the corresponding rxd pins in set to low, see figure 19 . the microcontroller is able to detect the low signal on rxd and to read the wake source out of the ?wake register interrupt? register (000) via spi. no interrupt is generated when coming out of sleep mode. the c can now switch the can transceiver into lin normal mode via spi to start communication. wake-up in sbc stop mode in sbc stop mode, if a wake-up is detected, it is signaled by the int output and by the ?wk linx? spi bit. it is also signaled by rxdlinx put to low.the microcontroller should set the device to sbc normal mode, there is no automatic transition to normal mode. in normal mode the transceiver can be enabled via spi. table 8 action due to a can wake up sbc mode sbc mode after wake vcc1c int rxd int. bit wk can sleep mode restart mode ramping up high low 1 stop mode stop mode on low 1) 1) when not masked via spi low 1 restart mode restart mode ramping up / on high low 1 fail-safe mode restart mode ramping up high low 1 normal mode normal mode on low 1) low 1
data sheet 45 rev. 1.0, 2009-05-26 TLE8262-2E lin transceiver 10.2.5 lin receive only mode in lin receive only mode (rxd only), the driver stage is de-activated but reception is still possible. this mode is accessible by an spi command. 10.2.6 lin flash mode in lin flash mode, the slope control mechanism is de-activated. this mode is accessible only in the sbc sw flash mode. a communication up to 100kbaud is possible. 10.3 lin cell mode with sbc mode table 9 shows the lin modes accessible in the different sbc modes. automatic transition from one lin mode to an other is only allowed in the same column. table 9 lin states based on sbc modes sbc mode lin mode init mode off normal mode off wake capable normal / low slope receive only sleep mode off wake capable restart mode off wake capable stop mode off wake capable fail-safe mode wake capable sw flash mode flash
data sheet 46 rev. 1.0, 2009-05-26 TLE8262-2E lin transceiver figure 19 timing during transition from sbc sleep to sbc normal mode 10.3.1 transition from sbc normal to sleep / stop mode it is recommended to first set the lin wake capable mode before setting the sbc sleep or stop mode to avoid missing a wake up event. the reason is identical to the can behavior. for additional information, see chapter 8.3.1 . do not change the transciever setting with the same spi command that is used to sent the device to sleep mode. 10.4 application information 10.4.1 bus short to gnd feature the lin transceiver has a feature implemented to protect the battery from running out of charge in case of a bus short to gnd. when the lin transceiver is switched to wake capable or off, the internal pull-up resistor is switched off to prevent a large current from flowing to gnd. in addition, the transceiver only wakes up on a dominant-to- recessive edge on the lin bus, so with the bus shorted to gnd the transceiver does not wake up. 10.4.2 oscillator tolerance as required by lin 2.1, an oscillator clock tolerance < 2% for the protocol handler is possible with lin transceiver. 10.4.3 lin specification the device fulfills the physical layer specification of lin 2.1. the device fulfills the physical layer specification sae j2602-2. v busx v cc 1c rxd sbc normal mode t wu bus idle wake pattern communication starts reset (ro) lin w k from sleep to nor mal .vsd sbc sleep mode sbc restart mode t rdx t t t t spi command lin wake capable mode lin waked lin normal mode
data sheet 47 rev. 1.0, 2009-05-26 TLE8262-2E lin transceiver 10.5 failure detection all failures are reported in the spi diagnostic encoder except the txd time-out feature, reported as txd shorted to gnd and over temperature, which is not reported. in case of failure, the transceiver is automatically switched to the lin receive only mode. the reactivation of the transmitter appears only after the microcontroller has requested it via spi, except the over temperature. in this particular case, the transmitter is reactivated after a transition from dominant to recessive. 10.5.1 txd time-out feature if the txd signal is dominant for a time t > t txd_to , the txd time-out function deactivates the transmission of the signal at the bus. this is done to prevent the bus from being permanently blocked due to an error. the transmission is released by sending the spi command for lin normal mode. refer to figure 20 . . figure 20 txd time-out diagram 10.5.2 bus dominant clamping if the lin bus signal in dominant for a time t > t lin_to , a bus dominant clamping is detected. the lin transceiver is switched to receive only mode. the failure is signaled via spi. if the bits are not masked, the int pin is set to low. for operation the transceiver needs to be switched back to normal mode via spi. 10.5.3 txd to rxd short circuit feature similar to the txd time-out, a txd to rxd short circuit would also block the bus communication. to avoid this, the lin transceiver has txd to rxd short circuit detection. this failure is reported to the diagnostic frame of the spi. the transmitter is automatically inhibited and is reactivated after an spi command. 10.5.4 overtemperature figure 21 shows how the transmission stage is deactivated and activated again. the driver stages are protected against overtemperature. exceeding the shutdown temperature results in deactivation of the driving stages. nevertheless, the sbc can still receive messages via the rxd output, by setting automatically the lin into lin receive only mode. to avoid a bit failure after cooling down, the signals can be transmitted again only after a dominant to recessive edge at txd. an overtemperature condition causes the transmission stage to deactivate. after the overtemperature condition is no longer present, transmission is reactivated after the txd bus signal has changed to recessive level. the failure is not indicated in the spi and doesn?t generate any interrupt. t txd lin t v cc1c v bus txd time -out interrupt gnd t txd_to lin txd timeout .vsd spi setting : lin normal mode
data sheet 48 rev. 1.0, 2009-05-26 TLE8262-2E lin transceiver figure 21 release of the transmission after overtemperature 10.5.5 permanent rxd recessive clamping if the rxd signal is permanently recessive (for example, shorted to v cc1c ), although there is a message sent on the bus, the host microcontroller of this transceiver could start a message at any time, because the bus appears to be idle. to prevent this node from disturbing communication on the bus, the sbc offers permanent rxd recessive clamping. if the rxd signal is permanently recessive, the failure is diagnosed and the transmitter is deactivated as long as the error occurs. the transmitter is reactivated only after a spi command. t failure overtemp t on txd lin v lin t recessive dominant v cc1c overtemperature gnd off r d
data sheet 49 rev. 1.0, 2009-05-26 TLE8262-2E lin transceiver 10.6 electrical characteristics v s = 6 to 18 v 1) ; r l = 500 ? ; t j = -40 c to +150 c; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. pos. parameter symbol limit values unit test condition min. typ. max. receiver output rxdx push pull 10.6.1 high level output voltage v rxd,h 0.8 v cc1c ??v lin normal mode i rxd(lin) = -1.6 ma; v bus = v s 10.6.2 low level output voltage v rxd,l ??0.2 v cc1c v lin normal mode i rxd(lin) = 1.6 ma; v bus = 0 v transmission input txdx 10.6.3 high level input voltage threshold v txd,h ??0.7 v cc1c v lin normal mode recessive state 10.6.4 input hysteresis v txd,hys ?0.12 v cc1c ?v 3) 10.6.5 low level input voltage threshold v txd,l 0.3 v cc1c ??v lin normal mode dominant state 10.6.6 pull-up resistance r td 20 40 80 k ? v txd = 0 v
data sheet 50 rev. 1.0, 2009-05-26 TLE8262-2E lin transceiver bus receiver busx 10.6.7 receiver threshold voltage, recessive to dominant edge v bus,rd 0.42 v s 0.45 v s ?v lin normal mode 10.6.8 receiver dominant state v bus,dom ??0.42 v s v lin normal mode (lin 2.1 param. 17) 10.6.9 receiver threshold voltage, dominant to recessive edge v bus,dr ?0.55 v s 0.58 v s v lin normal mode 10.6.10 receiver recessive state v bus,rec 0.58 v s ??v lin normal mode (lin 2.1 param. 18) 10.6.11 receiver center voltage v bus,c 0.475 v s 0.5 v s 0.525 v s v lin normal mode (lin2.1 param. 19) 10.6.12 receiver hysteresis v bus,hys 0.07 v s 0.1 v s 0.175 v s v lin normal mode v bus,hys = v bus,rec - v bus,dom (lin2.1 param. 20) 10.6.13 wake-up threshold voltage v bus,wk 0.40 v s 0.5 v s 0.6 v s v lin wake capable mode 10.6.14 dominant time for bus wake-up t wk,bus 30 ? 150 s lin wake capable mode 10.6 electrical characteristics (cont?d) v s = 6 to 18 v 1) ; r l = 500 ? ; t j = -40 c to +150 c; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. pos. parameter symbol limit values unit test condition min. typ. max.
data sheet 51 rev. 1.0, 2009-05-26 TLE8262-2E lin transceiver bus transmitter busx 10.6.15 bus serial diode voltage drop v serdiode 0.4 0.7 1.0 v lin normal mode v txd = v cc1c 10.6.16 bus recessive output voltage v bus,ro 0.8 v s ? v s v lin normal mode v txd = v cc1c 10.6.17 bus dominant output voltage v bus,do ??1.2v lin normal mode v txd = 0 v; v s = 7v; r l = 500 ? ; ??2.0v lin normal mode v s = 18 v; r l = 500 ? ; 10.6.18 bus dominant output voltage v bus,do 0.6 ? ? v lin normal mode v txd = 0 v; v s = 7v; r l = 1k ? ; 0.8 ? ? v lin normal mode v s = 18 v; r l = 1 k ? ; 10.6.19 bus short circuit current i bus,sc 40 100 150 ma lin normal mode v bus = 13.5 v; (lin2.1 param. 12) 10.6.20 leakage current i bus,lk -1000 -450 ? a v s = 0 v; v bus = -12 v; (lin2.1 param. 15) ??5a v s = 0 v; v bus = 18 v; (lin2.1 param. 16) -1 ? ? ma v s = 18 v; v bus = 0 v; (lin2.1 param. 13) ??5a v s = 8 v; v bus = 18 v; (lin2.1 param. 14) 10.6.21 bus pull-up resistance r bus 20 30 47 k ? lin normal mode (lin2.1 param. 26) 10.6.22 lin output current i bus -60 -30 -5 a lin wake capable / off mode; v s = 18 v; v bus = 0v 10.6 electrical characteristics (cont?d) v s = 6 to 18 v 1) ; r l = 500 ? ; t j = -40 c to +150 c; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. pos. parameter symbol limit values unit test condition min. typ. max.
data sheet 52 rev. 1.0, 2009-05-26 TLE8262-2E lin transceiver dynamic transceiver characteristics busx 10.6.30 propagation delay, bus dominant to rxd low t d(l),r ?16s v cc1c = 5 v; c rxd = 20 pf; (lin2.1 param. 31) 10.6.31 propagation delay, bus recessive to rxd high t d(h),r ?16s v cc1c = 5 v; c rxd = 20 pf; (lin2.1 param. 31) 10.6.32 receiver delay symmetry t sym,r -2 ? 2 s t sym,r = t d(l),r - t d(h),r ; (lin2.1 param. 32) 10.6.34 txd dominant time-out t txd_to 61220msv txd = 0 v 10.6.35 bus dominant time-out t lin_to 61220ms 3) 10.6.36 txd dominant time-out recovery time t torec ?10?s 3) 10.6.37 duty cycle d1 (for worst case at 20 kbit/s) tduty1 0.396 ? ? lin normal slope mode; duty cycle 1 2) th rec (max) = 0.744 v s; th dom (max) =0.581 v s ; v s = 7.0 ? 18 v; t bit = 50s; d1 = t bus_rec(min) /2 t bit ; (lin2.1 param. 27) 10.6.38 duty cycle d2 (for worst case at 20 kbit/s) tduty2 ? ? 0.581 lin normal slope mode; duty cycle 2 2) th rec (min)= 0.422 v s ; th dom (min)= 0.284 v s v s = 7.6 ? 18 v; t bit = 50s; d2 = t bus_rec(max) /2 t bit ; (lin2.1 param. 28) 10.6 electrical characteristics (cont?d) v s = 6 to 18 v 1) ; r l = 500 ? ; t j = -40 c to +150 c; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. pos. parameter symbol limit values unit test condition min. typ. max.
data sheet 53 rev. 1.0, 2009-05-26 TLE8262-2E lin transceiver 10.6.39 duty cycle d3 (for worst case at 10.4 kbit/s) low slope mode t duty3 0.417 ? ? lin low slope mode; duty cycle 3 2) th rec (max) = 0.778 v s; th dom (max) =0.616 v s ; v s = 7.0 ? 18 v; t bit = 96s; d3 = t bus_rec(min) /2 t bit ; (lin2.1 param. 29) 10.6.40 duty cycle d4 (for worst case at 10.4 kbit/s) low slope mode t duty4 ? ? 0.590 lin low slope mode; duty cycle 4 2) th rec (min)= 0.389 v s ; th dom (min)= 0.251 v s v s = 7.6 ? 18 v; t bit = 96s; d4 = t bus_rec(max) /2 t bit ; (lin2.1 param. 30) 10.6.41 lin input capacitance 15 pf 3) 1) lin specification is defined between 6 v and 18 v only. 2) bus load conditions concerning lin spec 2.0 c bus , r bus = 1 nf, 1 k ? / 6.8 nf, 660 ? / 10 nf, 500 ? 3) not subject to production test, specified by design 10.6 electrical characteristics (cont?d) v s = 6 to 18 v 1) ; r l = 500 ? ; t j = -40 c to +150 c; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. pos. parameter symbol limit values unit test condition min. typ. max.
data sheet 54 rev. 1.0, 2009-05-26 TLE8262-2E supervision functions 11 supervision functions 11.1 reset function 11.1.1 description the reset output pin ro provides information to the microcontroller, for example, in the event that the output voltage has fallen below the undervoltage threshold v rt1/2/3 . when connecting the sbc to battery voltage, the reset signal remains low initially. when the output voltage v cc1c has reached the reset threshold v rt1,r , the reset output ro remains low for the reset delay time t rd1 . after that the ro is released to high. a reset can also occur due to faulty watchdog refresh.see chapter 11.2 . the reset threshold as well as the reset delay time can be adjusted via spi. the ro pin has an integrated pull-up resistor. 11.1.2 reset diagnosis the ro pin is diagnosed for both short circuit to v ccx and gnd. depending on the configuration, in case of ro failure, the sbc goes to sbc fail-safe or restart mode and activate the limp home output. in case of short circuit to gnd, it is detected in any sbc mode except sbc restart mode. at the falling edge of the ro, when supposed to be high, the sbc enters automatically the sbc restart mode. if after the t rd and ro relaxation, the ro pin is still low, then the sbc detects the clamping to low failure. the microcontroller is in permanent reset. in case of short circuit to v ccx , the sbc cannot detect the short circuit before a reset should occur. so reset clamped is detected when the sbc goes to sbc restart mode or during init mode. 11.1.3 reset timing figure 22 reset timing diagram t rd1 t lw sbc init ro spi t v cc v rtx undervoltage t rdx sbc normal t t t lw t < t rr t rr t cw sbc restart sbc normal spi init res_per_8264.vsd t cw t ow wd trigger t cw t ow wd trigger spi init
data sheet 55 rev. 1.0, 2009-05-26 TLE8262-2E supervision functions 11.1.4 reset from outside if the reset pin ro is pulled to low from outside while no reset low is issued by the sbc, the device goes to restart mode. in restart mode an reset is issued by the sbc, the ro pin is set to low for the time t rd1 or t rd2 . if the ro pin is pulled to low for longer time reset clamped is detected. 11.2 watchdog two different watchdogs are possible in the sbc. it can be either a window watchdog or a time-out watchdog. the watchdog can also be inhibited in sbc stop mode and sbc sw flash mode via spi. the watchdog timing is programmed via spi command. as soon as the watchdog is activated, the timer starts running and the watchdog must be served. please refer to table 10 to match the sbc modes with the watchdog modes. the default setting for the watchdog is time-out watchdog with a 256 ms timer. the long open window allows the microcontroller to run its initialization sequences and then to trigger the watchdog via the spi. the watchdog is served by a spi bit and should toggle with the correct frequency. the default value is a 0, so the first trigger bit must be a 1. in case of a watchdog reset, the watchdog immediately starts with a long open window when entering sbc normal mode. with the reset the watchdog bit is set to 0, so the first watchdog trigger after reset is a change to 1. in sbc software development mode, no reset is generated due to watchdog failure, if a watchdog failure occurs it is indicated by the spi reset bit and via int pin. all watchdog modes are accessible in regards to the normal operation modes. table 10 watchdog functionality by sbc modes sbc mode watchdog mode remarks init mode watchdog programmable; watchdog is not active. init mode should be left in less than 256 ms (see chapter 13 ) normal mode wd programmable; time-out or window watchdog ? software flash mode mode is fixed sbc retains the set-up as in the mode before entering the software flash mode stop mode mode is fixed sbc retains the set up as in the mode before entering the stop mode sleep mode off sbc does not retain the set-up. fail-safe mode off sbc does not retain the set-up restart mode off sbc will start default watchdog setting (256ms time-out watchdog) when entering normal mode.
data sheet 56 rev. 1.0, 2009-05-26 TLE8262-2E supervision functions 11.2.1 time-out watchdog the time-out watchdog is an easier and less secure type of watchdog. compared to the window watchdog there is no closed window existing. the watchdog trigger can be done any time within the watchdog time. a watchdog trigger is detected as a write access to the ?wd refresh? within the spi control word. the bit needs to be toggle (transition high to low or low to high) within the watchdog window. the trigger is accepted when the csn input becomes high. a correct watchdog trigger starts a new window. the period is selected via the window watchdog timing bit field in the range of 16 ms to 1024 ms. for the safe trigger area the tolerance of the oscillator has to be taken into consideration, so the safe trigger time is below 90% of the programmed watchdog time. it is possible to refresh the watchdog with any spi programming with the mode selection normal, stop, sw flash or read only. should the trigger signal not meet the window, depending on the configuration, the sbc will go to sbc restart mode or to fail-safe mode. a watchdog reset is created by setting the reset output ro low. in config 1 and config 3 the watchdog starts again in normal mode with the default watchdog setting (256ms time-out watchdog). the watchdog failure can be read at the bits rm0, rm1, lh0, lh1, lh2 via spi. 11.2.2 window watchdog a watchdog trigger is detected as a write access to the ?wd refresh? within the spi control word. the bit needs to be toggle (transition high to low or low to high) in the open window. the trigger is accepted when the csn input becomes high. a correct watchdog trigger results in starting the window watchdog by a closed window with a width of typically 50% of the selected window watchdog reset period. this period, selected via the window watchdog timing bit field, is in the range of 16 ms to 1024 ms. this closed window is followed by an open window, with a width of typical 50% of the selected period. from now on, the microcontroller must serve the watchdog by periodically toggling the watchdog bit. this bit toggling access must meet the open window. the tolerance of the oscillator has to be taken into consideration, so the safe window to trigger the watchdog is from 55% to 90% of the programmed window watchdog time. it is possible to refresh the watchdog with any spi programming with the mode selection normal, stop, sw flash or read only. a correct watchdog service immediately results in starting the next closed window (see figure 23 , safe trigger area). should the trigger signal not meet the open window, depending on the configuration the sbc will go to sbc restart mode or to fail-safe mode. a watchdog reset is created by setting the reset output ro low (see figure 24 ). in config 1 and config 3 the watchdog starts again in normal mode with the default watchdog setting (256ms time-out watchdog). the watchdog failure can be read at the bits rm0, rm1, lh0, lh1, lh2 via spi.
data sheet 57 rev. 1.0, 2009-05-26 TLE8262-2E supervision functions figure 23 window watchdog definitions figure 24 window watchdog timing diagram for config 1 and config 3 11.2.3 changing the watchdog settings the settings of the watchdog can be changed during the operation of the watchdog. the change is done with a spi programming into the watchdog configuration register. the new setting is programmed together with a valid watchdog trigger according to the old settings. the timer with the new settings starts with this spi command. the toggling of the ?wd refresh? bit needs to be continued (transition high to low or low to high) with the new settings. if the new settings were not valid, the watchdog will continue with the old settings and generate a ?wrong wd set? interrupt. closed window open window t cwmin t / [t wdper ] t wd t owmax safe trigger area t cwmax t owmin 0.45 1.1 0.9 0.55 un- certainty uncertainty w d1 _per .vsd 1.0 window watchdog timing (spi) t wdr watchdog timer reset normal operation time-out (too long) timeout (too short) normal operation ro wd refresh bit t t normal operation t cw t ow t lw t cw t ow t cw +t ow t lw t cw t cw t ow t cw t ow t lw wd2_per.vsd
data sheet 58 rev. 1.0, 2009-05-26 TLE8262-2E supervision functions 11.2.4 inhibition of the watchdog during sbc stop mode and sbc sw flash mode, it is possible to deactivate the watchdog. to avoid unwished deactivation of the watchdog, a special protocol has to be followed, prior deactivating the watchdog. please refer to figure 25 . in the case the exact process below is not respected, the sbc remains in the previous state, and an interrupt is generated (if not inhibited), and the wrong wd set bit in the spi is set. when the microcontroller requests the sbc to go back to sbc normal mode, the watchdog is reactivated. the watchdog settings that were valid before entering stop mode with watchdog off are valid. the watchdog timer starts with entering normal mode. in case window watchdog was selected the watchdog starts with a closed window. when setting the wd refresh bit to 0 for the command that sends the device to normal mode the first watchdog trigger is a change to 1. as in stop mode the watchdog settings can not be changed, it is also not possible to change the watchdog settings with the command that sets the sbc from stop mode into normal mode. figure 25 inhibition of the watchdog during sbc stop mode, when the cyclic wake feature is used and the watchdog is not disabled, it is necessary that the microcontroller acknowledges the interrupt by reading the spi wake register before the next cyclic wake occures. otherwise, a reset is performed by setting the sbc to sbc restart mode. sbc init mode (256ms max after reset relaxation) wd conf wd not active sbc normal mode wd conf wd active sbc stop mode wd off spi cmd wd trig first battery connection (por) and config0 not active cyclic wk on / off sbc normal mode spi cmd = sbc stop mode & wd off & wd trigger spi cmd = sbc normal mode & wd off & wd trigger wd off sbc sw flash mode spi cmd = sbc sw flash mode &,wd off & wd trigger inhibition of the w d .vsd wd active cyclic wk on / off spi cmd = sbc sw flash mode &,wd off
data sheet 59 rev. 1.0, 2009-05-26 TLE8262-2E supervision functions 11.3 electrical characteristics v s = 5.5 v to 28 v; t j = -40 c to +150 c; sbc normal mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. pos. parameter symbol limit values unit test condition min. typ. max. reset generator; pin ro 11.3.1 reset threshold voltage, v rt1,f 4.5 4.65 4.75 v default setting, vcc falling v rt1,r 4.6 4.75 4.85 v default setting, vcc rising v rt2,f 3.5 3.65 3,75 v spi option;vcc falling v rt2,r 3.6 3.75 3,85 v spi option; vcc rising v rt3,f 3.2 3.35 3.45 v spi option; v s 4 v; vcc falling v rt3,r 3.3 3.45 3.55 v spi option; v s 4 v, vcc rising reset threshold voltage headroom v rt1_hr 250 ? ? mv default setting 1) 1) headroom between actual output voltage on v cc1c and reset threshold voltage for falling vcc. v rt2_hr 1.25 ? ? v spi option; 1) v rt3_hr 1.55 ? ? v spi option; v s 4 v 1) 11.3.2 reset threshold hysteresis v rt,hys 20 100 200 mv - 11.3.3 reset low output voltage v ro ?0.20.4v i ro = 1 ma for v cc1c = v rt1/2/3 ; i ro = 200 a for v rt1/2/3 > v cc1c 1 v 11.3.4 reset high output voltage v ro 0.7 x v cc1c ? v cc1c + 0.3 v v i ro = -20a 11.3.5 reset pull-up resistor r ro 10 20 40 k ? v ro = 0 v 11.3.6 reset reaction time t rr 41026s v cc1c < v rt1/2 to ro = l 11.3.7 reset delay time t rd1 4.5 5.0 5.5 ms default spi setting; after power-on-reset t rd2 450 500 550 s spi setting option watchdog generator 11.3.8 long open window t lw ?256?ms 2) default setting 2) specified by design; not subject to production test. tolerance defined by internal oscillator tolerance f clksbc . internal oscillator 11.3.9 internal oscillator tolerance f clksbc -10 0 10 % ?
data sheet 60 rev. 1.0, 2009-05-26 TLE8262-2E interrupt function 12 interrupt function 12.1 interrupt description the interrupt pin has a general purpose function to point out to the microcontroller either a wake up, a failure condition or the switch on of a voltage regulator. table 11 shows the possible interrupt sources in the device, and figure 26 gives the hardware set-up. the interrupt function is designed to inform the microcontroller of any wake- up event, overtemperature or overtemperature pre-warning as well as other failures. these events turn the int pin to active low. all interrupt sources can be masked via a spi bit, then no interrupt is generated for this event. for failures on under-voltage the interrupt is dual-sensitive. this means that an interrupt is generated when the failure appears, as well as when the failure disappears. for failures on over-temperature, communication failures and voltage regulator over current and undervoltage, the dedicated spi interrupt bit indicated first the interrupt source and then the state of the device. so, the bit is set to failure 1 at the event, and remains latched at least until the microcontroller reads the bit. for the sbc failure (wrong wd setting, reset, fail spi) and wake events, the int indicates only an event and the bit is cleared with a dedicated spi read. the int pin is released when an spi read is done to interrupt register 000 with a ?read only? command, or after interrupt time out t intto . if the interrupt cause was a wake event, the interrupt bit can be read in interrupt register 000 and the bit is cleared. if it was an other interrupt source the bit int is set, and interrupt register 001 and 010 need to be read. with a ?read only?command the event triggered interrupt bits are cleared. the int bit will be set to ?0? when all bits in interrupt register 001 and 010 are set to ?0?. if an interrupt is masked (bit set to ?0?) only the interrupt does not occur, the interrupt bit in the spi is shown. figure 26 shows a simplified diagram of the int output. in init mode before ro goes high the int pin is used to set the configuration of the device to config 1/3 or config 2/4, see chapter 14 . figure 26 interrupt block diagram table 11 interrupt sources interrupt sources int activation spi bit state temperature over temperature pre-warning v cc1c rising otp v cc1c event / state over temperature v cc2 rising ot v cc2 over temperature hs can rising ot hscan communication failure can failure rising can failure 1..0 can bus event/ state lin failure rising linx failure 1..0 voltage regulator interrupt block.vsd interrupt logic int time out v c c 1 c r in t
data sheet 61 rev. 1.0, 2009-05-26 TLE8262-2E interrupt function 12.1.1 interrupt for switching on vcc2 and vcc3 the interrupt for vcc2 and vcc3 are generated when the spi command for switching on the voltage regulator is executed. the interrupt bit is set to ?1? and can be cleared with a read only command after the under voltage threshold is reached. if the read only is done before the reset threshold is reached, the interrupt bit can not be cleared as the undervoltage condition is still present. in this case a second interrupt can be issued for releasing the undervoltage condition. in case of a short to gnd on vcc2 or vcc3 the interrupt for switching on the voltage regulator is issued, but the c can not clear the interrupt bit as the voltage regulator does not reach the undervoltage threshold. 12.1.2 example of interrupt events and read-out the examples show single interrupt events. spi read is done with ?read only?. the shown interrupts are not masked. watchdog trigger is not shown in the examples. the interrupt uv_vcc2 that is generated by switching on v cc2 is shown in figure 27 . the interrupt is sensitive on rising event only. undervoltage at v cc2 (except during switch off 1) ) rising and falling uv _vcc2 event / state undervoltage at v cc3 (except during switch off 1) ) rising and falling uv _vcc3 over current at v cc3 (except during inhibition) rising i cc3 > i cc3max voltage at v cc2 (during switch on 1) ) rising uv _vcc2 event voltage at v cc3 (during switch on 1) ) rising uv _vcc3 sbc failure spi data corrupted rising spi fail event reset (sbc sw development only) rising reset wrong watchdog setting rising wrong wd set wake wake at can rising wk can event wake at lin rising wk linx wake at wk rising wk wk pin 1..0 cyclic wk rising cyclic wk 1) when v cc2/3 is switched off no interrupt is generated due to the undervoltage at v cc2/3 . when switching on v cc2/3 an interrupt is generated when the command is sent to the sbc via spi. table 11 interrupt sources interrupt sources int activation spi bit state
data sheet 62 rev. 1.0, 2009-05-26 TLE8262-2E interrupt function figure 27 interrupt vcc2 switch-on. vcc2 switched off by spi int pin conf. select 000 conf. select 001 conf. select 002 int bit uv_v cc2 spi d i pr ogr am m i ng read only mode select bits 111 0 0 0 0 optional x x x x interrupt_ switchon_ vcc2 .vsd rising event (vcc2 above limit) is shown vcc2 1 1 x x x x required optional vcc2 switched on by spi
data sheet 63 rev. 1.0, 2009-05-26 TLE8262-2E interrupt function the interrupt uv_vcc2 that is generated by an under-voltage on v cc2 is shown in figure 28 . the interrupt is sensitive on rising and falling event and the interrupt bit also shows the state of the device and function. figure 28 interrupt v cc2 under-voltage. the interrupt ot_vcc2 that is generated by an over temperature on v cc2 is shown in figure 29 . the interrupt is sensitive on rising event and the interrupt bit also shows the state of the device and function. figure 29 interrupt vcc2 over temperature. undervoltage on vcc2 int pin conf. select 000 conf. select 001 conf. select 002 int bit uv_v cc2 1 1 spi di programming read only mode select bits 111 1 1 0 0 x x x x required optional x x x x interrupt_uv_vcc2.vsd falling event (vcc2 below limit), rising event (vcc2 above limit) as well as state is shown vcc2 1 1 x x x x required optional ot_v cc2 overtemperature on vcc2 int pin conf. select 000 conf. select 001 conf. select 002 int bit ot_v cc2 1 1 spi di progr amming read only mode select bits 111 1 1 0 0 x x x x required optional x x x x interrupt_ot_vcc2.vsd rising event (apperance of overtemperature ) is shown, as well as the state.
data sheet 64 rev. 1.0, 2009-05-26 TLE8262-2E interrupt function 12.2 interrupt timing figure 30 illustrates the interrupt timing. the int output is set low as soon as an interrupt condition occurs. the int pin is released after a spi interrupt buffer read out command, that is performed with a read only command (111) to register (000). in case consecutive interrupt sources are indicated before the spi read out, only one int low will be raised but the spi read out will indicate the interrupt sources. a time-out feature is implemented. the int pin can be active low only for the time t intto . afterwards, the int pin is released but the int source is still valid or present in the spi register. between two activations of the int, there is at least a delay of t intto . if an interrupt occurs in the meantime, the information is stored and the int will go low after t into . the int pulse width is at minimum t int . figure 30 interrupt timing 12.3 interrupt modes with sbc modes the interrupt function is possible only in sbc normal and stop mode. after an sbc restart mode, all interrupt sources are enabled. 12.4 interrupt application information by default, all interrupt sources are activated. please refer to the dedicated chapter for the definition of the interrupt. the int output is active for at least t int , even if the corresponding interrupt register is read out immediately after the interrupt event occurs. if no spi read is done after the interrupt is generated (int pin low) the int output becomes active (int pin high) again after t intto . if two interrupt cases occur after each other and the spi read (with read-only) is done after the second interrupt case, both interrupt bits are cleared. although the interrupt bits for both interrupt cases are cleared the second interrupt will be issued by int pin low. this can lead to an interrupt where all interrupt bits are read as ?0?. interrupt source 1 interrupt source 2 int output t t t inactive active inactive active spi read out t int to interupt timing.vs d spi read out t intto t int spi read out t intto t intto spi read out
data sheet 65 rev. 1.0, 2009-05-26 TLE8262-2E interrupt function 12.5 electrical characteristics . v s = 5.5 v to 28 v; t j = -40 c to +150 c; sbc normal mode; all voltages with respect to ground; positive current defined flowing into pin unless otherwise specified. pos. parameter symbol limit values unit test condition min. typ. max. interrupt output; pin int 12.5.1 interrupt delay time-out t intto 5.4 6 6.6 ms ? 12.5.2 int pulse width t int 10 ? ? s 1) 1) not subject to production test, specified by design. 12.5.3 int low output voltage v intol ?0.20.4v i int = 1 ma 12.5.4 int high output voltage v intoh 0.7 x v cc1c ? v cc1c + 0.3 v v i int = -20a 12.5.5 int pull-up resistor r int 10 20 40 k ? v int = 0 v configuration select; pin int 12.5.6 int config low input voltage v cfglo 0.3 x v cc1c ??v? 12.5.7 int config high input voltage v cfghi ? ? 0.7 x v cc1c v? 12.5.8 int config pull down r cfg ?250?k ? ?
data sheet 66 rev. 1.0, 2009-05-26 TLE8262-2E limp home 13 limp home 13.1 description the limp home outputs are a very useful way to control safety critical functions independent of the microcontroller, such as turning on or off critical load during a microcontroller failure. 13.2 limp home output the limp home output is an active low open drain transistor, please refer to figure 31 ; therefore, it is necessary to connect at least an external pull-up resistor at. the limp home output is activated due to a failure condition or via spi, see chapter 13.3 . if v s is below v lhuv , the limp home cannot be activated and remains as a high impedance. figure 31 limp home block diagram 13.2.1 limp home side indicators output the lh_si output is similar to the limp home output. the output is pulsed to f lhsi frequency with d si and designed to provide the side indicators frequency. the lh_si function is active when the limp home is active. figure 32 limp home lh_si block diagram 13.2.2 lh_pl (pulsed light) output the lh_pl/test pin is an output pin shared with the test pin function. during sbc init mode, the pin is used as an input, in all other modes, the pin is an output. the output is pulsed to f lhpl frequency with a duty cycle of d pl (20% low, 80% high impedance), designed to dim the 27w stop lights into an 5w rear light. refer to figure 33 . the lh_pl function is activated when the limp home is active. in sbc init mode, the lh_pl is inhibited, to avoid a wrong set of the sbc into sbc software development mode. limp home.vsd limp home logic limp home limp home_lhsi.vsd limp home logic limp home lh_si
data sheet 67 rev. 1.0, 2009-05-26 TLE8262-2E limp home figure 33 lh_pl/ test block diagram 13.2.3 test pin the test pin is used to set the sbc chip into sbc software development mode. when the test pin is connected to gnd, the sbc starts in sbc software development mode. when the pin is left open, or connected to v s the sbc starts into normal operation. please refer to figure 3 . the test pin has an integrated pull-up resistor (switched on only during sbc init mode) to prevent the sbc device from starting in sbc software development mode during normal life of the vehicle, as for example when the battery has been disconnected. to avoid disturbance, the test pin is monitored during the init mode (from the time v s > v uvon until init mode is left). if the pin is low for the init mode time, software development mode is reached. the mode is stored during the complete time where v s is above v uvoff . it means to leave software development mode, the sbc must go back to sbc off mode. lh_ pl / test v s r lh_ pl sbc init mode limp home lh_pl_test.vsd t test t lh _pl
data sheet 68 rev. 1.0, 2009-05-26 TLE8262-2E limp home 13.3 activation of the limp home output the reason to activate the limp home pins and the consequences are listed in table 12 and table 13 . 13.4 release of the limp home output when limp home is activated via spi command, then it is released via spi command. this is useful for diagnosis purpose for example. otherwise, the limp home outputs are released only in sbc normal mode with the following conditions: after the device has been set to sbc restart mode, automatically entering sbc normal mode, a successful watchdog trigger must be sent via spi. at this point, the limp home outputs remain active. then the microcontroller needs to send by spi command the deactivation of the limp home. 13.5 v cc1c undervoltage time-out a v cc1c undervoltage time-out condition is given, when 1) the v cc1c output voltage is below the reset threshold ( v rt1 , v rt2 , v rt3 ), 2) v s is higher then the threshold ( v sthuv1 , v sthuv2 , v sthuv3 ) and 3) the condition is valid longer then the v cc1c under voltage time-out ( t vcc1uvto ). a v cc1c undervoltage time-out will sent the device into fail-safe mode. limp home output stag will be activated (for v s > v lhuv ) figure 34 gives an example of the limp home output activation, due to a v cc1c undervoltage time-out. table 12 limp home, function of the sbc mode sbc mode limp home outputs init mode off normal mode off on via spi on if it was on until the successful watchdog setting and deactivation via spi. stop mode unchanged sleep mode unchanged restart mode unchanged fail-safe mode on sw flash mode unchanged table 13 automatic activation of limp home output sbc mode reason init mode init time-out (t initto ) normal mode 1st watchdog failure (config 1/2) 2nd watchdog failure (config 3/4) restart mode reset output permanent short circuit to v cc1c reset output permanent short circuit to gnd v cc1c undervoltage time-out any mode if previously turned on in sbc normal mode, via spi command v cc1c thermal shutdown
data sheet 69 rev. 1.0, 2009-05-26 TLE8262-2E limp home figure 34 v cc1c undervoltage time-out timing t vcc1c t gnd ro t vs t rdx v rtx undervoltage time out.vsd v rtx t vcc1uvto sbc sleep sbc restart sbc normal sbc restart sbc fail safe t rr t limp home v sthuvx gnd wake up
data sheet 70 rev. 1.0, 2009-05-26 TLE8262-2E limp home 13.6 electrical characteristics v s = 5.5 v to 28 v; t j = -40 c to +150 c; sbc normal mode; all voltages with respect to ground; positive current defined flowing into pin unless otherwise specified. pos. parameter symbol limit values unit test condition min. typ. max. limp home; 13.6.1 watchdog edge count difference to set limp home activated n lh ?1 2 ? ? with spi set. default setting 13.6.2 limp home low output voltage (active) v lhlo ?0.20.4vi lh = 1ma 13.6.3 limp home high output current (inactive) i lhhi 0 ?2av lh = 28v 13.6.4 init time-out t initto ?256?ms 1) 13.6.5 v cc1c under voltage time-out t vcc1uvto 900 1024 1150 ms 13.6.6 v s threshold for v cc1c under voltage time-out ( v s needs to be above, to activate v cc1c under voltage time-out) v sthuv1 5.3 ? 6.3 v v rt1 default setting v sthuv2 4.3 ? 5.3 v v rt2 spi option v sthuv3 4.0 ? 5.0 v v rt3 spi option 13.6.7 threshold for limp home minimum v s v lhuv 4.5 ? 5.5 v ? 13.6.8 limp home v s voltage hysteresis v lhuvhys ?0.2?v? lh _si; 13.6.9 limp home side indicator frequency f lhsi 1.125 1.25 1,375 hz ? 13.6.10 limp home side indicator duty cycle d si ?50?%? lh_pl/test 13.6.11 high level input voltage threshold v test,hi ?? 3v? 13.6.12 input hysteresis v test,hys 100 300 700 mv ? 13.6.13 low level input voltage threshold v test,lo 1? ?v? 13.6.14 pull-up resistor r test 20 40 80 k ? v lh_pl/test = 0v sbc init mode 13.6.15 limp home pulsed light frequency f lh_pl 90 100 110 hz ? 13.6.16 limp home pulsed light duty cycle d pl -20-%? 1) not subject to production test, specified by design.
data sheet 71 rev. 1.0, 2009-05-26 TLE8262-2E configuration select 14 configuration select 14.1 configuration select the configuration select is used to set the device for two different sbc behaviors; please refer to chapter 4.2.1 for detailed information. depending on the requirements of the application, the v cc1c is switched off and the device goes to fail-safe mode in case of watchdog fail (1 or 2 fail) or reset clamped. to turn v cc1c off (config 2/4), the int pin is not connected to a pull up resistor externally. in case the v cc1c is not switched off (config 1/3) the int pin is connected to v cc1c with a pull up resistor. the configuration is only read during init mode, after that the configuration is stored. 14.2 config hardware descriptions in init mode before the ro pin goes high the int pin is pulled to low with a weak pull down resistor r cfg , the pull up resistor r int is switched off. when v cc1c is high, above the reset threshold v rt1 and before the ro pin goes high the level on the int pin is monitored to select the configuration. with ro going high in init mode the pull up resistor r int is switched on. figure 35 gives the electrical equivalents to the configuration function of the int pin. figure 35 config logic diagram electrical characteristics are listed in chapter chapter 12.5 interrupt block_config.vsd interrupt logic int time out v c c 1 c r in t configuration logic r cfg
data sheet 72 rev. 1.0, 2009-05-26 TLE8262-2E serial peripheral interface 15 serial peripheral interface 15.1 spi description the 16-bit wide control input word is read via the data input sdi, which is synchronized with the clock input clk supplied by the microcontroller. the output word appears synchronously at the data output sdo (see figure 36 ). the transmission cycle begins when the chip is selected by the input csn (chip select not), low active. after the csn input returns from low to high, the word that has been read in becomes the new control word. the sdo output switches to tri-state status (high impedance) at this point, thereby releasing the sdo bus for other use. the state of sdi is shifted into the input register with every falling edge on clk. the state of sdo is shifted out of the output register after every rising edge on clk. the number of received input clocks is supervised by a modulo-16 operation and the input / control word is discarded in case of a mismatch. this error is flagged in the following spi output by a ?high? at the data output (sdo pin, bit fo) before the first rising edge of the clock is received. the spi of the sbc is not daisy chain capable. figure 36 spi data transfer timing 15.2 corrupted data in the spi data input when the microcontroller send a wrong spi command to the sbc, the sbc ignores the information. wrong spi command can be either a number of bits different of 16, the mode selection (ms2..0) = 000 or requesting to go to an sbc mode which is not allowed by the state machine, for example from sbc stop mode to sbc sw flash mode. in that case, an interrupt is generated (if not inhibited) and the bit spi fail is set. since the spi data is corrupted, the next spi output data will remain the former one (the information is then repeated). 0 0 + 1 2 3 4 5 6 7 8 9 10 15 1 + 0 1 2 3 4 5 6 11 12 13 14 7 8 9 10 15 fi fi - csn high to low: sdo is enabled. status information transferred to output shift register csn low to high: data from shift register is transferred to output functions sdi: will accept data on the falling edge of clk signal sdo: will change state on the rising edge of clk signal actual status 11 12 13 14 actual data new data new status sdo sdi csn clk time time time time fo fo - 0 + 1 +
data sheet 73 rev. 1.0, 2009-05-26 TLE8262-2E serial peripheral interface 15.3 spi input data figure 37 16-bit spi input data / control word 15 14 13 12 11 10 8 9 7 6 5 4 3 2 0 1 mode selection bits configuration select configuration registers l.h. on/off input data normal sw flash sleep 000 001 010 011 100 101 000 010 reset delay window /time out watchdog timing bit position: 10 .. 6 res. can 1 110 111 011 001 lin 10.4k wd on/off chk sum spi data input tle8262.vsd not valid read only fail safe lsb msb ms0 ms1 ms2 cs0 cs1 v cc2 on/off restart stop ti. out / win . wd to lh res. can 0 v cc3 on/off wk pin on/off rt1 rt0 cyclic wk on /off 100 110 111 101 cs2 res. wk 0 wk pin res. wk lin1 wk can reserved test 2 lh 1 lh 2 lh 0 test 1 test 0 wd refresh res. res. reserved interrupt mask register set to 1 res. res. lin1 1 lin 1 0 uv v cc2 ot v cc2 reset fail spi uv v cc 3 otp v cc 1c ot hs can wrong wd set res. lin1 failure 0 res. res. can bus lin1 failure 1 can failure 1 can failure 0 res. i cc3 > i cc3max wk 1 wk pin res.
data sheet 74 rev. 1.0, 2009-05-26 TLE8262-2E serial peripheral interface 15.4 spi output data figure 38 16-bit spi output data / control word figure 39 16-bit spi output data / control word 15.5 spi data encoding 15.5.1 wd refresh bit / wk state the wd refresh bit is used to trigger the watchdog. the first trigger should be a 1 , and then a 0 . for more details, please refer to chapter 11.2 . the wk state bit gives the voltage level at the wk pin. a 1 indicates a high level, a 0 a low level. 15 14 13 12 11 10 8 9 7 6 5 4 3 2 0 1 mode selection bits configuration select configuration registers l.h. on/off output data normal sw flash sleep 000 001 010 011 100 101 000 010 reset delay window /time out watchdog timing bit position: 10 .. 6 110 111 011 001 lin 10.4k wd on/off chk sum spi_settings_out_tle8262.vsd fail safe reserved lsb msb ms0 ms1 ms2 cs0 cs1 v cc2 on/off restart stop ti. out / win. wd to lh v cc3 on/off rt1 rt0 cyclic wk on/off 100 110 111 101 cs2 uv v cc2 ot v cc2 reset fail spi uv v cc 3 otp v cc 1c ot hs can wrong wd set res. lin1 failure 0 res. res. can bus lin1 failure 1 can failure 1 can failure 0 res. res. wk 0 wk pin cyclic wk res. wk lin1 wk can reserved test 2 lh 1 lh 2 lh 0 test 1 test 0 res. res. int rm1 wk state rm0 status or interrupt event register set to 1 res. can 1 res. can 0 wk pin on /off res. res. lin1 1 lin 1 0 i cc3 > i cc3max init wk 1 wk pin
data sheet 75 rev. 1.0, 2009-05-26 TLE8262-2E serial peripheral interface 15.5.2 sbc configuration setting and read out 15.5.2.1 mode selection bits and configuration select table 14 lists the encoding of the possible sbc mode. except sbc restart and init mode which are most of time entered automatically, all others sbc mode are accessible on request of the microcontroller. the microcontroller should send the correct mode selection bits to set the sbc in the respective mode. the output indicates the sbc mode where the sbc currently is or was, depending on the situation. table 15 lists the eight possible configuration selection. some are related to event or state of the different part of the sbc, others are used to configure the sbc in the application specific set up. table 14 mode selection bits ms2 ms1 ms0 data input data output 0 0 0 not valid (the complete spi word is ignored) show the device was in init previous spi data 0 0 1 set the sbc to sbc restart mode. (in sw flash mode only) show the device was in restart previous spi data 0 1 0 set the sbc to software flash mode show the device is sbc software flash mode 0 1 1 set the sbc to sbc normal mode show the device is in sbc normal mode 1 0 0 set the sbc to sbc sleep mode show the device was in sbc sleep mode 1 0 1 set the sbc to sbc stop mode show the device is in sbc stop mode 1 1 0 set the sbc to sbc fail-safe mode (in sbc software development mode only) show the device was in sbc fail-safe mode 1 1 1 set the sbc to read only spi access. the configuration register needs to be selected. the spi information on sdo is provided in the same spi frame. no write access is done in this mode. bit 15 (watchdog) has to be served correctly. reserved table 15 configuration select encoder (for data input and output) cs2 cs1 cs0 configuration register select 0 0 0 wake register interrupt 0 0 1 sbc failure interrupt 0 1 0 communication failure interrupt 0 1 1 reserved 1 0 0 sbc configuration register 1 0 1 communication setup register 1 1 0 watchdog configuration register 1 1 1 limp home / diagnosis register
data sheet 76 rev. 1.0, 2009-05-26 TLE8262-2E serial peripheral interface 15.5.2.2 interrupt register encoder table 16 lists all interrupts the sbc can generates. the microcontroller should read the correct register to release the int pin. by default, all interrupt sources are enabled. the microcontroller can decide to inhibit a specific interrupt source. table 16 interrupt register encoder 1) cs bit name default value (input) default value (out) data input data output configuration select 000 (wake register interrupt) 000 wk can 1 0 interrupt enabled (1) disabled (0) for wake event on can wake on can (1) wklinx 1 0 interrupt enabled (1) disabled (0) for wake event on lin wake on linx (1) wk 1 wk pin wk 0 wk pin 11 00 interrupt enabled (1) disabled (0) for wake pin event. 00 no interrupt 10 interrupt for a low to high transition on wk 01 interrupt for high to low transition on wk 11 interrupt for both high to low and low to high on wk wake on wk pin 00 no wake 10 interrupt for a low to high transition on wk 01 interrupt for high to low transition on wk 11 interrupt for both high to low and low to high on wk cyclic wk n.a 0 n.a cyclic wk (1) int n.a 0 n.a indicates that there is a status bit or uncleared event in configuration select 001 and/or 010. if set read the two register
data sheet 77 rev. 1.0, 2009-05-26 TLE8262-2E serial peripheral interface configuration select 001 (sbc failure interrupt) 001 otp_v cc1c 1 0 interrupt enabled (1) disabled (0) for temperature pre-warning v cc1c temperature pre warning (1) ot_hscan 1 0 interrupt enabled (1) disabled (0) for temperature shutdown hs can temperature shutdown (1) ot_v cc2 1 0 interrupt enabled (1) disabled (0) for temperature shutdown v cc2 temperature shutdown (1) uv_v cc3 1 0 interrupt enabled (1) disabled (0) for undervoltage detection or due to back to normal voltage undervoltage detection on vcc3 (1) spi fail 1 0 interrupt enabled (1) disabled (0) for spi corrupted data. spi input corrupted data (1) reset 1 0 interrupt enabled (1) disabled (0) for reset information (only in sbc software development mode) reset (1) (only in sbc software development mode) wrong wd set 1 0 interrupt enabled (1) disabled (0) for incorrect watchdog setting incorrect wd programming for data output uv v cc2 1 0 interrupt enabled (1) disabled (0) for undervoltage detection at v cc2 under voltage detected at v cc2 i cc3 > i cc3max 1 0 interrupt enable (1) disabled (0) for over current at v cc3 over current detected at v cc3 configuration select 010 (communication failure interrupt) 010 can failure 1 can failure 0 n.a 1 0 0 interrupt enabled (1) disabled (0) for can failure can failure refer to table 17 can bus 1 0 interrupt enabled (1) disabled (0) for can bus failure can bus failure detected (1) linx failure 1 linx failure 0 n.a 1 0 0 interrupt enabled (1) disabled (0) for lin failure lin failure. refer to table 17 1) a value of 0 will set the sbc into the opposite state. table 16 interrupt register encoder (cont?d) 1) cs bit name default value (input) default value (out) data input data output
data sheet 78 rev. 1.0, 2009-05-26 TLE8262-2E serial peripheral interface 15.5.2.3 can / lin failure encoder table 17 describes the encoding of the possible internal can and lin failures. 15.5.2.4 configuration encoder table 18 lists the configuration register of the sbc. the microcontroller can change the settings. if no settings are changed the default values are used. the current value can be read on the spi data out. table 17 can / lin failure encoder can / linx 1 failure can / linx 0 failure fault 00 no failure 0 1 txd shorted to gnd or bus dominant clamped 1 0 rxd shorted to v cc 1 1 txd shorted to rxd table 18 configuration encoder configuration select bit name default value (input) default value (out) state configuration select 100 (s bc configuration register) 100 rt10 01 01 reset threshold setting. please refer to table 19 reset delay 1 1 long reset window v cc3 on /off 0 0 v cc3 is activated (1) wk pin on / off 1 1 the wake pin will wake the sbc v cc2 on / off 0 0 v cc2 is activated (1) lh on / off 0 0 limp home output state. activated (1) when entry condition is met. cyclic wk on / off 0 0 activation (1) of the cyclic wake wd to lh 1 1 watchdog failure to limp home active. 0 = only one watchdog failure brings to limp home activated. 1 = two consecutive watchdog failures bring to limp home activated.
data sheet 79 rev. 1.0, 2009-05-26 TLE8262-2E serial peripheral interface 15.5.2.5 reset encoder table 19 lists the three possible reset thresholds. please also refer to chapter 11.3 to get the exact voltage threshold. 15.5.2.6 sbc watchdog encoder table 20 list the 32 possible watchdog timer. configuration select 101 (sbc communication set up register) 101 lin 10.4k 1 1 lin cells are in lin low slope mode (1) can 1.0 00 00 the can cell is in: 00 = can off 01 = can is wake capable 10 = can receive only mode 11 = can normal mode linx 1.0 00 00 the lin cell is in: 00 = lin off 01 = lin is wake capable 10 = lin receive only mode 11 = lin normal mode configuration select 110 (sbc watchdog register) 110 ti. out / win. 1 1 time-out watchdog is activated set to 1 1 1 bit is reserved and fix set to ?1?. set to 1 in sw. wd on / off 1 1 watchdog is activated chk sum 1 1 check sum of the bit 13...6 in case the chk sum is wrong, the device remains in previous valid state. configuration select 111 (limp home / diagnosis register) 111 - reserved for input for output, refer to table 21 , table 22 and table 23 table 19 reset encoder rt1 rt0 threshold selected 0 0 not valid. device remains at previous threshold 0 1 vrt1 (default setting at sbc init), 10vrt2 11vrt3 table 18 configuration encoder configuration select bit name default value (input) default value (out) state chksum bit13 bit6 =
data sheet 80 rev. 1.0, 2009-05-26 TLE8262-2E serial peripheral interface 15.5.3 sbc diagnostic encoder the sbc offers diagnostics information. the encoding of the different possible failures are listed in the following table. the description apply only to data output. 15.5.3.1 reason for restart and reset reason for reset, without activation of the limp home and the way it is encoded are summed up in table 21 . the bits are cleared by reading the register with read-only command. when coming from sleep mode or fail safe mode the bits are cleared. table 20 watchdog encoder bit 10...6 decimal calculation (ms) timer (ms) 00000 0 (n+1) 16 n = decimal value of setting 16 00001 1 32 00010 2 48 ... ... ... 01111 15 256 (default setting) 10000 16 n 48 - 464 304 10001 17 352 ... ... ... 11110 30 976 11111 31 1024 table 21 reason to enter sbc restart mode without limp homelimp home activation rm1 rm0 cause for entering sbc restart mode 0 0 no reset has occurred or limp home activated 0 1 undervoltage on v cc1c 1 0 first watchdog failure (config 3 and 4) or no acknowledge of the cyclic wake-up 1 1 spi command in sbc software flash mode or reset low from outside
data sheet 81 rev. 1.0, 2009-05-26 TLE8262-2E serial peripheral interface 15.5.3.2 limp home failure encoder table 22 describes the encoding of all possible reason to activate automatically the limp home output. bits are set back to ?000? when switching limp home off via spi. 15.5.3.3 test pin and failure to limp home configuration read out the sbc allows to read the hardware setting of the configuration that is done via the int pin, as well as the test pin and the wd to lh bit. table 23 describes the encoding of these informations. table 22 limp home failure diagnosis lh2 lh1 lh0 failure 1) 000 no failure 001 v cc1c undervoltage time-out 0 1 0 one watchdog failure (config 1 and 2) 0 1 1 two consecutive watchdog failures (config 3 and 4) 1 0 0 init mode time-out 1 0 1 temperature shutdown at v cc1c 1 1 0 reset clamped 111 reserved table 23 test pin and sbc configuration test2 test1 test0 test read out 1) 1) refer also to chapter 4.2.1 000 v cc1c remains on in sbc restart mode after one watchdog failure (config 1) 001 v cc1c is off in sbc fail-safe mode after one watchdog failure (config 2) 010 v cc1c remains on in sbc restart mode after two watchdog failures (config 3) 011 v cc1c is off in sbc fail-safe mode after two watchdog failures (config 4) 1 0 0 software development mode. in case of watchdog failure v cc1c remains on, no reset is generated and restart mode or fail-safe mode are not entered. 1 0 1 software development mode. in case of watchdog failure v cc1c remains on, no reset is generated and restart mode or fail-safe mode are not entered. 1 1 0 software development mode. in case of watchdog failure v cc1c remains on, no reset is generated and restart mode or fail-safe mode are not entered. 1 1 1 software development mode. in case of watchdog failure v cc1c remains on, no reset is generated and restart mode or fail-safe mode are not entered.
data sheet 82 rev. 1.0, 2009-05-26 TLE8262-2E serial peripheral interface 15.6 spi output data 15.6.1 first spi output data since the spi output data is sent when the sbc is receiving data, the output data are dependent of the previous spi command, if no read only command is used. under some conditions there is no ?previous command?. table 24 gives the first spi output data that is sent to the microcontroller when entering sbc normal mode, depending on the mode where the sbc was before receiving the first spi command. . table 24 first spi output data frame previous sbc mode mode selection bits (ms2...0) configuration select (cs 2..0) sleep mode sleep mode wake register interrupt 1) 1) this does not clear the bits. it will be reset when the microcontroller requests the read out fail-safe mode fail-safe mode limp home register 1) restart mode when failure and config 1 / 3 restart mode limp home register 1) restart mode when microcontroller has sent to restart mode restart mode sbc configuration register sbc init mode init mode sbc configuration register
data sheet 83 rev. 1.0, 2009-05-26 TLE8262-2E serial peripheral interface 15.6.2 read only command in the mode selection bits a read only can be selected. the read only access clears the int bits that are selected in the configuration select (some interrupt bits show a state, and can not be cleared with a spi read). with this spi command no write access is done to the sbc, and the mode of the sbc is not changed. the watchdog can also be triggered with a read only command. the read only command delivers the information requested with the configuration select in the same spi command on the sdo pin. as all other spi commands deliver the requested information with the next spi command. figure 40 shows an example of a read only access. the bits are shown with lsb first, on the left side in difference to the register description. figure 40 read only command figure 41 shows an example of an spi write access in normal mode for comparison. the requested information is sent out with the next spi command. figure 41 write command wk state 0 1 2 3 4 5 7 6 8 9 10 11 12 13 15 14 configuration registers di ms0ms1ms2cs0cs1cs2 wd refresh configuration select mode selection bits 0 1 2 3 4 5 7 6 8 9 10 11 12 13 15 14 configuration registers di ms0 ms1 ms2 cs0 cs1 cs2 wd refresh configuration select mode selection bits 0 1 2 3 4 5 7 6 8 9 10 11 12 13 15 14 configuration registers do ms0ms1ms2cs0cs1cs2 configuration select mode selection bits 1 1 1 0 0 0 x x x x x x x x x x wk state 0 1 2 3 4 5 7 6 8 9 10 11 12 13 15 14 configuration registers do ms0 ms1 ms2 cs0 cs1 cs2 configuration select mode selection bits 1 1 0 1 0 0 x x x x x x x x x x 1 1 0 0 0 0 x x x x x x x x x x 1 1 0 1 1 1 x x x x x x x x x x time wk state 0 1 2 3 4 5 7 6 8 9 10 11 12 13 15 14 configuration registers di ms0ms1ms2cs0cs1cs2 wd refresh configuration select mode selection bits 0 1 2 3 4 5 7 6 8 9 10 11 12 13 15 14 configuration registers di ms0 ms1 ms2 cs0 cs1 cs2 wd refresh configuration select mode selection bits 0 1 2 3 4 5 7 6 8 9 10 11 12 13 15 14 configuration registers do ms0ms1ms2cs0cs1cs2 configuration select mode selection bits 1 1 0 0 0 0 x x x x x x x x x x wk state 0 1 2 3 4 5 7 6 8 9 10 11 12 13 15 14 configuration registers do ms0 ms1 ms2 cs0 cs1 cs2 configuration select mode selection bits 1 1 0 0 0 0 x x x x x x x x x x 1 1 0 1 0 0 x x x x x x x x x x 1 1 0 1 1 1 x x x x x x x x x x time
data sheet 84 rev. 1.0, 2009-05-26 TLE8262-2E serial peripheral interface 15.7 electrical characteristics v s = 5.5 v to 28 v; t j = -40 c to +150 c; sbc normal mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. pos. parameter symbol limit values unit test condition min. typ. max. spi interface; logic inputs sdi, clk and csn 15.7.1 h-input voltage threshold v ih ? ? 0.7 x v cc1c v? 15.7.2 l-input voltage threshold v il 0.3 x v cc1c ??v? 15.7.3 hysteresis of input voltage v ihy 0.12 x v cc1c v? 1) 15.7.4 pull-up resistance at pin csn r icsn 20 40 80 k ? v csn = 0.7 v cc1c 15.7.5 pull-down resistance at pin sdi and clk r iclk/sdi 20 40 80 k ? v sdi/clk = 0.2 v cc1c 15.7.6 input capacitance at pin csn, sdi or clk c i ?10- pf-1) logic output sdo 15.7.7 h-output voltage level v sdoh v cc1c - 0.4 v cc1c - 0.2 ?v i doh = -1.6 ma 15.7.8 l-output voltage level v sdol ?0.20.4v i dol = 1.6 ma 15.7.9 tri-state leakage current i sdolk -10 ? 10 a v csn = v cc1c ; 0 v < v do < v cc1 15.7.10 tri-state input capacitance c sdo ?1015pf1) data input timing 1) 15.7.11 clock period t pclk 250 ? ? ns ? 15.7.12 clock high time t clkh 125 ? ? ns ? 15.7.13 clock low time t clkl 125 ? ? ns ? 15.7.14 clock low before csn low t bef 125 ? ? ns ? 15.7.15 csn setup time t lead 250 ? ? ns ? 15.7.16 clk setup time t lag 250 ? ? ns ? 15.7.17 clock low after csn high t beh 125 ? ? ns ? 15.7.18 sdi set-up time t disu 100 ? ? ns ? 15.7.19 sdi hold time t diho 50 ? ? ns ?
data sheet 85 rev. 1.0, 2009-05-26 TLE8262-2E serial peripheral interface figure 42 spi timing diagram note: numbers in drawing correlate to the last 2 digits of the pos. number in the electrical characteristics table. 15.7.20 input signal rise time at pin sdi, clk and csn t rin ? ? 50 ns ? 15.7.21 input signal fall time at pin sdi, clk and csn t fin ? ? 50 ns ? 15.7.22 delay time for mode change from normal mode to sleep mode t fin ?? 10s? 15.7.23 csn high time t csn(high) 10 ? ? s - data output timing 1) 15.7.24 sdo rise time t rsdo ?3080nsc l = 100 pf 15.7.25 sdo fall time t fsdo ?3080nsc l = 100 pf 15.7.26 sdo enable time t ensdo ? ? 50 ns low impedance 15.7.27 sdo disable time t dissdo ? ? 50 ns high impedance 15.7.28 sdo valid time t vasdo ? ? 60 ns c l = 100 pf 1) not subject to production test; specified by design 15.7 electrical characteristics (cont?d) v s = 5.5 v to 28 v; t j = -40 c to +150 c; sbc normal mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. pos. parameter symbol limit values unit test condition min. typ. max. csn clk di do 13 12 not defined lsb m sb flag lsb m sb 15 26 28 18 16 27 23 19 14 17
data sheet 86 rev. 1.0, 2009-05-26 TLE8262-2E application information 16 application information note: the following information is given only as a hint for the implementation of the device and should not be regarded as a description or warranty of a certain functionality, condition or quality of the device. figure 43 application example for a body controller module t 1 c 1 c 2 c 3 r 1 d 2 r 2 c 4 v s bus1 s 1 vbat r 5 wk c 7 r 7 canh c 8 r 8 canl r 9 v ss v dd csn clk sdi sdo c txd lin 1 rxd lin1 txd can rxd can int gnd vbb cs sclk si so ic1 lhi in0 in1 in2 in3 in4 in5 vdd vbat csn clk sdo sdi txd lin 1 rxd lin 1 txd can rxd can limp home v cc 1c c 9 v dd c 10 r 10 bus 1 wk v s v cc3shunt v cc3base v cc 3ref reset int ro v dd c 11 v cc2 v cchscan c 14 gnd v io v cc gnd ic2 v cc gnd ic3 v dd v s v s logic state machine application _information _ tle8262 -2e .vsd device ground c 12 canh split canl s 2 can cell c 13 d 1 vbat vbat v s tle8262-2 d 5 r 12 v s t2 v s t3 v s t4 lh_ si lh_pl/test
data sheet 87 rev. 1.0, 2009-05-26 TLE8262-2E application information note: this is a very simplified example of an application circuit and bill of material. the function must be verified in the actual application. table 25 bills of material ref. option vendor value purpose capacitance c1 y kemet 68f optional depending on application cut off battery spike c2 y 100nf emc c3 n murata 10f ceramic cap low esr stability of the v cc3 c5 n 1nf oem dependent lin master termination c7 y 22nf 50v emc c8 y 47nf oem dependent improve split pin stability c9 y 10f buffer of the v cc1c depending on load. (c) c10 n 100nf stability of the v cc1c c11 n 10f can transceiver dependent buffering of the v cc2 for can transceiver c12 y 100nf improve stability of the logic c13 y 100nf improve stability of the logic c14 y 100nf improve stability of the logic resistance r1 n 220m ? v cc3 current measurement for i cc3 400ma max r3 y 1k ? / oem dependent lin master termination r5 y 1k ? wetting current of the switch r7 y 60 ? / oem dependent can bus termination r8 y 60 ? / oem dependent can bus termination r9 y 10k ? limit the wk pin current in iso pulses r10 y 500 ? insulation of the vdd supply r12 y 47k ? set config 1/3. if not connected config 2/4 is selected
data sheet 88 rev. 1.0, 2009-05-26 TLE8262-2E application information active components t1 n on semi mjd253 power element of v cc3 infineon bcp52-16 alternative power element of v cc3, current limit to be adapted r1 to be changed. t2 n infineon bcr191w high active limp home t3 n infineon bcr191w high active limp home t4 n infineon bcr191w high active limp home d1 n infineon bas 3010a reverse polarity protection d3 n infineon bas70 06 (dual) bas70 (single) requested by lin norm. protect the application in reverse polarity. c n infineon xc2xxx micro-controller ic1 y infineon spoc - bts5672e high side switches ic2 y infineon tle 6254-3g low speed can ic3 y infineon tle 6251ds high speed can table 25 bills of material ref. option vendor value purpose
data sheet 89 rev. 1.0, 2009-05-26 TLE8262-2E application information 16.1 zthja curve figure 44 zthja curve, function of cooling area figure 45 board set-up board set-up is done according to jesd 51-3, single layer fr4 pcb 70 m . zthja curves.vsd 0 10 20 30 40 50 60 0,00001 0,0001 0,001 0,01 0,1 1 10 100 1000 10000 time (s) zth-ja [k/w] zth-ja(ch4; 600) zth-ja(ch4; 300) zth-ja(ch4; 100) zth-ja(ch4; footprint) 600mm2 cooling area 300mm2 cooling area 100mm2 cooling area minimum footprint pcb set up.vsd
data sheet 90 rev. 1.0, 2009-05-26 TLE8262-2E application information 16.2 hints for sbc factory flash mode the mode is used during production of the module to flash the c. the idea is that the c is not supplied from the sbc but from an external 5v power supply. the reset of the c that is connected to the ro pin of the sbc can be driven from an external source and the sbc does not give a reset signal. also no interrupt at the pin int and no signal on the spi sdo pin is generated by the sbc. the spi pins can be driven externally. the mode is reached by applying 5v to the v cc1c pin and no voltage to the vs pin. the vs pin will show a voltage of about 4.5v because of the internal diode from v cc1c to v s . the current drawn at vs must not exceed the maximum rating of i vs,max = -500ma. the function is designed for ambient temperature. in case the v s was supplied before going to ff mode, the voltage on pin v s must be set below 3 v before applying 5v to v cc1c (discharging the c) figure 46 application hint for factor flash mode application_ ff_mode _2.vsd vs v cc1 c v ss v dd csn clk sdi sdo c txd lin1 rxd lin1 txd lin2 rxd lin2 txd lin3 rxd lin3 txd can rxd can int csn clk sdo sdi txd lin1 rxd lin1 txd lin2 rxd lin2 txd lin3 rxd lin3 txd can rxd can reset int ro c vbat other devices i vs 5v reset signal not supplied not supplied the current flowing to other devices from vs should be limited to not exceed the maximum ratings. internal supply
data sheet 91 rev. 1.0, 2009-05-26 TLE8262-2E application information 16.3 esd tests tests for esd robustness according to iec61000-4-2 ?gun test? (150pf, 330 ? ) have been performed. the results and test condition is available in a test report. the values for the test are listed in table 27 below. table 26 pin in factory flash mode pin level comment vs typ. 4.5v voltage output from sbc. no voltage applied from external. vcc1c 5v 2% to be applied from external ro pull-up resistor can be driven from external int pull-up resistor can be driven from external if required lh high impedance can be driven from external if required sdo high impedance can be driven from external if required clk, sdi pull-down resistor can be driven from external if required csn pull-up resistor can be driven from external if required txdcan, txdlin1, txdlin2, txdlin3 pull-up resistor can be driven from external if required rxdcan, rxdlin1, rxdlin2, rxdlin3 high impedance can be driven from external if required table 27 esd ?gun test? performed test result unit remarks esd at pin canh, canl, busx, vs versus gnd > 8 kv positive pulse 1) 1) esd susceptibility ?esd gun? contact discharge (r=330ohm c=150pf) (din en 61000-4-2) tested according lin emc 1.3 test specification and ict emc evaluation of can transceiver. tested by external test house (ibee zwickau, emc test report nr. 06-02-09a) esd at pin canh, canl, busx, vs versus gnd < -8 kv negative pulse
data sheet 92 rev. 1.0, 2009-05-26 TLE8262-2E package outline 17 package outline figure 47 pg-dso-36-38 (leadframe a6901-003) ;) note: for the sbc product family the package pg-dso-36-38 with the leadframe a6901-c003 is used. green product (rohs compliant) to meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations, the universal system basis chip is available as a green product. green products are rohs-compliant (i.e pb-free finish on leads and suitable for pb-free soldering according to ipc/jedec j-std- 020). pg-dso-36-24, -38, -41, -42, -50-po v09 exposed diepad index marking 1) does not include plastic or metal protrusion of 0.15 max. per side 2) does not include dambar protrusion of 0.05 max. per side 3) distance from leads bottom (= seating plane) to exposed diepad index marking 1 18 36 19 18 1 19 36 bottom view 0.65 17 x 0.65 = 11.05 ?.08 0.33 2) 3) a-b 0.17 m 36x c c c d 0.1 36x seating plane 0...0.10 stand off -0.2 2.45 2.55 max. 1.1 -0.2 7.6 1) 0.35 x 45? 0.7 ?.2 10.3 ?.3 +0.09 0.23 8? max. a d 1) 12.8 -0.2 b pg-dso-36-38 pg-dso-36-38 pg-dso-36-24, -41, -42 package a6901-c007 a6901-c003 a6901-c001 leadframe 5.2 7 7 4.6 pg-dso-36-50 a6901-c008 6.0 5.4 5.1 5.1 exposed diepad dimensions ejector mark 4) 4) excluding the mold flash allowance of 0.3 max per side ex ex ey ey for information about packages and types of packing, refer to the infineon internet page ?products?: http://www.infineon.com/products . dimensions in mm
data sheet 93 rev. 1.0, 2009-05-26 TLE8262-2E revision history 18 revision history version date parameter changes 1.0 2009-05-26 first rev. of data sheet
edition 2009-05-26 published by infineon technologies ag 81726 munich, germany ? 2009 infineon technologies ag all rights reserved. legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infineon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies components may be used in life-support devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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